ATxmega32D4 Atmel Corporation, ATxmega32D4 Datasheet - Page 153
![no-image](/images/manufacturer_photos/0/0/79/atmel_corporation_sml.jpg)
ATxmega32D4
Manufacturer Part Number
ATxmega32D4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega32D4
Flash (kbytes)
32 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
4
Twi (i2c)
2
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
14
Input Capture Channels
14
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega32D4-AU
Manufacturer:
Atmel
Quantity:
123
Part Number:
ATxmega32D4-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATxmega32D4-CU
Manufacturer:
Maxim
Quantity:
71
Company:
Part Number:
ATxmega32D4-MH
Manufacturer:
Atmel
Quantity:
1 910
Company:
Part Number:
ATxmega32D4-MH
Manufacturer:
Atmel
Quantity:
1 704
Part Number:
ATxmega32D4-MH
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
14.4
8210B–AVR–04/10
Dead Time Insertion
The Dead Time Insertion (DTI) unit enables generation of “off” time where both the non-inverted
Low Side (LS) and inverted High Side (HS) of the WG output is low. This “off” time is called
dead-time, and dead-time insertion ensure that the LS and HS does not switch simultaneously.
The DTI unit consists of four equal dead time generators, one for each of the capture or com-
pare channel in Timer/Counter 0.
time generator. The dead time registers that define the number of peripheral clock cycles the
dead time is going to last, are common for all four channels. The High Side and Low Side can
have independent dead time setting and the dead time registers are double buffered.
Figure 14-3. Dead Time Generator block diagram
As shown in
one for each peripheral clock cycle until it reaches zero. A non-zero counter value will force both
the Low Side and High Side outputs into their “off” state. When a change is detected on the WG
output, the Dead Time Counter is reloaded with the DTx register value according to the edge of
the input. Positive edge initiates a counter reload of the DTLS Register and a negative edge a
reload of DTHS Register.
WG output
Dead Time Generator
Figure 14-4 on page
D
Q
Edge Detect
V
Figure 14-3 on page 153
154, the 8-bit Dead Time Counter (dti_cnt) is decremented by
DTLSBUF
DTILS
LOAD
E
V
shows the block diagram of one dead
Counter ("dti_cnt")
DTHSBUF
= 0
DTIHS
XMEGA D
"dtls"
(To PORT)
"dths"
(To PORT)
153