ATxmega32D4 Atmel Corporation, ATxmega32D4 Datasheet - Page 193
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ATxmega32D4
Manufacturer Part Number
ATxmega32D4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega32D4
Flash (kbytes)
32 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
4
Twi (i2c)
2
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
14
Input Capture Channels
14
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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Company
Part Number
Manufacturer
Quantity
Price
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Part Number:
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Manufacturer:
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Part Number:
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Quantity:
20 000
17. SPI – Serial Peripheral Interface
17.1
17.2
8210B–AVR–04/10
Features
Overview
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The Serial Peripheral Interface (SPI) is a high-speed synchronous data transfer interface using
three or four pins. It allows fast communication between an XMEGA device and peripheral
devices or between several AVR devices. The SPI supports full duplex communication.
A device connected to the bus must act as a master or slave.The master initiates and controls all
data transactions. The interconnection between Master and Slave CPUs with SPI is shown in
Figure 17-1 on page
ator. The SPI Master initiates the communication cycle when pulling low the Slave Select (SS)
pin of the desired Slave. Master and Slave prepare the data to be sent in their respective Shift
Registers, and the Master generates the required clock pulses on the SCK line to interchange
data. Data is always shifted from Master to Slave on the Master Out - Slave In (MOSI) line, and
from Slave to Master on the Master In - Slave Out (MISO) line. After each data packet, the Mas-
ter can synchronize the Slave by pulling high the SS line.
Figure 17-1. SPI Master-slave Interconnection
The XMEGA SPI module is single buffered in the transmit direction and double buffered in the
receive direction. This means that bytes to be transmitted cannot be written to the SPI Data Reg-
ister before the entire shift cycle is completed. When receiving data, a received character must
be read from the Data register before the next character has been completely shifted in. Other-
wise, the first byte is lost.
Full-duplex, Three-wire Synchronous Data Transfer
Master or Slave Operation
LSB First or MSB First Data Transfer
Eight Programmable Bit Rates
End of Transmission Interrupt Flag
Write Collision Flag Protection
Wake-up from Idle Mode
Double Speed (CK/2) Master SPI Mode
193. The system consists of two shift Registers, and a Master clock gener-
XMEGA D
SHIFT
ENABLE
193