ATxmega32D4 Atmel Corporation, ATxmega32D4 Datasheet - Page 21
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ATxmega32D4
Manufacturer Part Number
ATxmega32D4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega32D4
Flash (kbytes)
32 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
4
Twi (i2c)
2
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
14
Input Capture Channels
14
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega32D4-AU
Manufacturer:
Atmel
Quantity:
123
Part Number:
ATxmega32D4-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATxmega32D4-CU
Manufacturer:
Maxim
Quantity:
71
Company:
Part Number:
ATxmega32D4-MH
Manufacturer:
Atmel
Quantity:
1 910
Company:
Part Number:
ATxmega32D4-MH
Manufacturer:
Atmel
Quantity:
1 704
Part Number:
ATxmega32D4-MH
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
4.5
4.6
4.7
4.7.1
4.8
8210B–AVR–04/10
Data Memory
Internal SRAM
EEPROM
I/O Memory
Data Memory Mapped EEPROM Access
The Data memory contains the I/O Memory, internal SRAM, optionally memory mapped
EEPROM and external memory if available. The data memory is organized as one continuous
memory section, as shown in
Figure 4-2.
I/O Memory, EEPROM and SRAM will always have the same start addresses for all XMEGA
devices. External Memory (if exist) will always start at the end of Internal SRAM and end at
address 0xFFFF.
The internal SRAM is mapped in the Data Memory space, always starting at hexadecimal
address location 0x2000. SRAM is accessed from the CPU by using the load (LD/LDS/LDD) and
store (ST/STS/STD) instructions.
XMEGA has EEPROM memory for non-volatile data storage. It is addressable either in as a sep-
arate data space (default), or it can be memory mapped and accessed in normal data space.
The EEPROM memory supports both byte and page access.
The EEPROM address space can optionally be mapped into the Data Memory space to allow
highly efficient EEPROM reading and EEPROM buffer loading. When doing this EEPROM is
accessible using load and store instructions. Memory mapped EEPROM will always start at
hexadecimal address location 0x1000.
The status and configuration registers for all peripherals and modules, including the CPU, are
addressable through I/O memory locations in the data memory space. All I/O locations can be
accessed by the load (LD/LDS/LDD) and store (ST/STS/STD) instructions, transferring data
between the 32 general purpose registers in the Register File and the I/O memory. The IN and
Data Memory Map
Figure 4-2 on page
Start/End
Address
0xFFFF
0x0000
0x1000
0x2000
Internal SRAM
Data Memory
I/O Memory
EEPROM
(Up to 4 KB)
(Up to 4 KB)
22.
XMEGA D
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