ATxmega32D4 Atmel Corporation, ATxmega32D4 Datasheet - Page 191
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ATxmega32D4
Manufacturer Part Number
ATxmega32D4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega32D4
Flash (kbytes)
32 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
4
Twi (i2c)
2
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
14
Input Capture Channels
14
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega32D4-AU
Manufacturer:
Atmel
Quantity:
123
Part Number:
ATxmega32D4-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATxmega32D4-CU
Manufacturer:
Maxim
Quantity:
71
Company:
Part Number:
ATxmega32D4-MH
Manufacturer:
Atmel
Quantity:
1 910
Company:
Part Number:
ATxmega32D4-MH
Manufacturer:
Atmel
Quantity:
1 704
Part Number:
ATxmega32D4-MH
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
16.10.6
8210B–AVR–04/10
ADDRMASK - TWI Slave Address Mask Register
• Bit 7:1 - ADDRMASK[7:1]: Read/Write Direction
These bits in the ADDRMASK register can act as a second address match register, or an
address mask register depending on the ADDREN setting.
If ADDREN is set to zero, ADDRMASK can be loaded with a 7-bit Slave Address mask. Each bit
in ADDRMASK can mask (disable) the corresponding address bit in the ADDR register. If the
mask bit is one the address match between the incoming address bit and the corresponding bit
in ADDR is ignored, i.e. masked bits will always match.
If ADDREN is set to one, ADDRMASK can be loaded with a second slave address in addition to
the ADDR register. In this mode, the slave will match on 2 unique addresses, one in ADDR and
the other in ADDRMASK.
• Bit 0- ADDREN: Address Enable
By default this bit is zero and the ADDRMASK bits acts as an address mask to the ADDR regis-
ter. If this bit is set to one, the slave address match logic responds to the 2 unique addresses in
ADDR and ADDRMASK.
Bit
+0x05
Read/Write
Initial Value
R/W
7
0
R/W
6
0
R/W
5
0
ADDRMASK[7:1]
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
XMEGA D
ADDREN
R/W
0
0
ADDRMASK
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