ATxmega32D4 Atmel Corporation, ATxmega32D4 Datasheet - Page 192
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ATxmega32D4
Manufacturer Part Number
ATxmega32D4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega32D4
Flash (kbytes)
32 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
4
Twi (i2c)
2
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
14
Input Capture Channels
14
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega32D4-AU
Manufacturer:
Atmel
Quantity:
123
Part Number:
ATxmega32D4-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATxmega32D4-CU
Manufacturer:
Maxim
Quantity:
71
Company:
Part Number:
ATxmega32D4-MH
Manufacturer:
Atmel
Quantity:
1 910
Company:
Part Number:
ATxmega32D4-MH
Manufacturer:
Atmel
Quantity:
1 704
Part Number:
ATxmega32D4-MH
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
16.11 Register Summary - TWI
16.12 Register Summary - TWI Master
16.13 Register Summary - TWI Slave
16.14 Interrupt Vector Summary
Table 16-9.
8210B–AVR–04/10
Address
Address
Address
+0x00
+0x01
+0x08
+0x00
+0x01
+0x02
+0x03
+0x04
+0x05
+0x06
+0x00
+0x01
+0x02
+0x03
+0x04
+0x05
Offset
0x00
0x02
Name
Name
Name
ADDRMASK
MASTER
STATUS
STATUS
CTRLC
SLAVE
CTRLA
CTRLB
CTRLA
CTRLB
TWI Interrupt vectors and their word offset addresses
BAUD
ADDR
ADDR
CTRL
DATA
DATA
MASTER_vect
SLAVE_vect
Bit 7
Bit 7
Bit 7
RIF
DIF
Source
–
–
–
–
INTLVL[1:0]
INTLVL[1:0]
Bit 6
Bit 6
Bit 6
APIF
WIF
–
–
–
–
Interrupt Description
TWI Master Interrupt vector
TWI Slave Interrupt vector
CLKHOLD
CLKHOLD
Bit 5
Bit 5
Bit 5
RIEN
DIEN
–
–
–
–
ADDRMASK[7:1]
Offset address for TWI Master
Offset address for TWI Slave
RXACK
RXACK
Bit 4
Bit 4
Bit 4
APIEN
WIEN
–
–
–
–
ADDR[7:0]
ADDR[7:0]
BAUD[7:0]
DATA[7:0]
DATA[7:0]
ARBLOST
ENABLE
ENABLE
Bit 3
Bit 3
Bit 3
COLL
–
–
–
TIMEOUT[1:0]
BUSERR
BUSERR
ACKACT
ACKACT
Bit 2
Bit 2
Bit 2
PIEN
–
–
SDAHOLD
TPMEN
Bit 1
Bit 1
Bit 1
QCEN
DIR
–
BUSSTATE[1:0]
CMD[1:0]
CMD[1:0]
ADDREN
XMEGA D
Bit 0
EDIEN
Bit 0
SMEN
Bit 0
SMEN
AP
–
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