ATxmega32D4 Atmel Corporation, ATxmega32D4 Datasheet - Page 157
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ATxmega32D4
Manufacturer Part Number
ATxmega32D4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega32D4
Flash (kbytes)
32 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
4
Twi (i2c)
2
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
14
Input Capture Channels
14
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Part Number:
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Manufacturer:
Atmel
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123
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Quantity:
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Part Number:
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Part Number:
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Quantity:
20 000
14.7.2
14.7.3
8210B–AVR–04/10
FDEMASK - Fault Detect Event Mask Register
FDCTRL - Fault Detection Control Register
• Bit 7:0 - FDEVMASK[7:0]: Fault Detect Event Mask
These bits enables the corresponding event channel as fault condition input source. Event from
all event channels will be ORed together allowing multiple sources to be used for fault detection
at the same time. When a fault is detected the Fault Detect Flag FDF is set and the fault detect
action (FDACT) will be performed.
• Bit 7:5 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 4 - FDDBD: Fault Detection on Debug Break Detection
By default, when this bit is cleared and the fault protection is enabled, and OCD break request is
treated as a fault. When this bit is set, an OCD break request will not trigger a fault condition.
• Bit 3 - Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write
this bit to zero when this register is written.
• Bit 2- FDMODE: Fault Detection Restart Mode
This bit sets the fault protection restart mode. When this bit is cleared Latched Mode is use, and
when this is set Cycle-by-Cycle Mode is used.
In Latched Mode the waveform output will remain in the fault state until the fault condition is no
longer active and the FDF has been cleared by software. When both of these conditions are
met, the waveform output will return to normal operation at the next UPDATE condition.
In Cycle-by-Cycle Mode the waveform output will remain in the fault state until the fault condition
is no longer active. When this condition is met, the waveform output will return to normal opera-
tion at the next UPDATE condition
• Bit 1:0 - FDACT[1:0]: Fault Detection Action
These bits define the action performed if a fault condition is detected, according to
Bit
+0x03
Read/Write
Initial Value
Bit
+0x02
Read/Write
Initial Value
R/W
R
7
–
0
7
0
R/W
R
6
–
0
6
0
R/W
R
5
–
0
5
0
.
FDDBD
R/W
R/W
4
0
FDEVMASK[7:0]
4
0
R/W
R
3
–
0
3
0
FDMODE
R/W
R/W
2
0
2
0
R/W
R/W
1
0
1
0
FDACT[1:0]
XMEGA D
R/W
R/W
0
0
0
0
Table
FDEMASK
FDCTRL
14-1.
157