ATxmega32D4 Atmel Corporation, ATxmega32D4 Datasheet - Page 177
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ATxmega32D4
Manufacturer Part Number
ATxmega32D4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega32D4
Flash (kbytes)
32 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
4
Twi (i2c)
2
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
14
Input Capture Channels
14
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega32D4-AU
Manufacturer:
Atmel
Quantity:
123
Part Number:
ATxmega32D4-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATxmega32D4-CU
Manufacturer:
Maxim
Quantity:
71
Company:
Part Number:
ATxmega32D4-MH
Manufacturer:
Atmel
Quantity:
1 910
Company:
Part Number:
ATxmega32D4-MH
Manufacturer:
Atmel
Quantity:
1 704
Part Number:
ATxmega32D4-MH
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
16.5
Figure 16-12. TWI Master Operation
8210B–AVR–04/10
SW
APPLICATION
TWI Master Operation
M1
Mn
SW
BUSY
Wait for
IDLE
Driver software
The master provides data
on the bus
Slave provides data on
the bus
Bus state
Diagram connections
M2
P
If a START condition is generated internally while in idle state the owner state is entered. If the
complete transaction was performed without interference, i.e. no collisions are detected, the
master will issue a STOP condition and the bus state changes back to idle. If a collision is
detected the arbitration is assumed lost and the bus state becomes busy until a STOP condition
is detected. A Repeated START condition will only change the bus state if arbitration is lost dur-
ing the issuing of the Repeated START.
The TWI master is byte-oriented with optional interrupt after each byte. There are separate inter-
rupts for Master Write and Master Read. Interrupt flags can also be used for polled operation.
There are dedicated status flags for indicating ACK/NACK received, bus error, arbitration lost,
clock hold and bus state.
When an interrupt flag is set, the SCL line is forced low. This will give the master time to respond
or handle any data, and will in most cases require software interaction.
TWI master operation. The diamond shaped symbols (SW) indicate where software interaction
is required. Clearing the interrupt flags, releases the SCL line.
The number of interrupts generated is kept at a minimum by automatic handling of most condi-
tions. Quick Command and Smart Mode can be enabled to auto trigger operations and reduce
software complexity.
IDLE
M3
S
ADDRESS
R/W
R/W
W
R
BUSY
A
A
A
M4
MASTER WRITE INTERRUPT + HOLD
MASTER READ INTERRUPT + HOLD
SW
SW
SW
SW
SW
A/A
A/A
A/A
A
BUSY
BUSY
Sr
Sr
P
P
IDLE
IDLE
DATA
M1
M2
M3
M4
M2
M3
Figure 16-12
DATA
XMEGA D
A/A
BUSY
shows the
M4
177