ATxmega32D4 Atmel Corporation, ATxmega32D4 Datasheet - Page 127
![no-image](/images/manufacturer_photos/0/0/79/atmel_corporation_sml.jpg)
ATxmega32D4
Manufacturer Part Number
ATxmega32D4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega32D4
Flash (kbytes)
32 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
4
Twi (i2c)
2
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
14
Input Capture Channels
14
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega32D4-AU
Manufacturer:
Atmel
Quantity:
123
Part Number:
ATxmega32D4-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATxmega32D4-CU
Manufacturer:
Maxim
Quantity:
71
Company:
Part Number:
ATxmega32D4-MH
Manufacturer:
Atmel
Quantity:
1 910
Company:
Part Number:
ATxmega32D4-MH
Manufacturer:
Atmel
Quantity:
1 704
Part Number:
ATxmega32D4-MH
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
12.6
12.6.1
12.6.2
12.6.3
12.6.4
8210B–AVR–04/10
Counter Operation
Normal Operation
Event Action Controlled Operation
32-bit Operation
Changing the Period
Dependent of the mode of operation, the Counter is cleared, reloaded, incremented, or decre-
mented at each Timer/Counter clock input.
In Normal Operation the Counter will count in the direction set by the Direction (DIR) bit for each
clock until it reaches TOP or BOTTOM. When TOP is reached when up-counting, the counter
will be set to zero when the next clock is given. When down-counting the Counter is reloaded
with Period Register value when BOTTOM is reached.
Figure 12-6. Normal Mode of Operation
As shown in
write access has higher priority than count, clear, or reload and will be immediate. The direction
of the Counter can also be changed during normal operation.
Normal operation must be used when using the counter as timer base for the capture channels.
The Event Selection and Event Action settings can be used to control the Counter from the
Event System. For the Counter the event actions can be selected to:
Two Timer/Counters can be used together to enable 32-bit counter operation. By using two
Timer/Counters the overflow event from one Timer/Counter (least significant timer) can be
routed via the Event System and used as clock input for another Timer/Counter (most significant
timer).
The Counter period is changed by writing a new TOP value to the Period Register. If double
buffering is not used, any period update is immediate as shown in
• Event system controlled Up/Down counting.
• Event system controlled Quadrature Decode counting.
CNT
DIR
MAX
Figure 12-6
TOP
BOT
changing the counter value while the counter is running is possible. The
CNT written
Figure 12-7 on page
XMEGA D
"update"
128.
127