ATxmega32D4 Atmel Corporation, ATxmega32D4 Datasheet - Page 91
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ATxmega32D4
Manufacturer Part Number
ATxmega32D4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega32D4
Flash (kbytes)
32 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
4
Twi (i2c)
2
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
14
Input Capture Channels
14
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega32D4-AU
Manufacturer:
Atmel
Quantity:
123
Part Number:
ATxmega32D4-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATxmega32D4-CU
Manufacturer:
Maxim
Quantity:
71
Company:
Part Number:
ATxmega32D4-MH
Manufacturer:
Atmel
Quantity:
1 910
Company:
Part Number:
ATxmega32D4-MH
Manufacturer:
Atmel
Quantity:
1 704
Part Number:
ATxmega32D4-MH
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
9.7
9.7.1
8210B–AVR–04/10
Registers Description
CTRL – Watchdog Timer Control Register
• Bits 7:6 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bits 5:2 - PER[3:0]: Watchdog Timeout Period
These bits determine the Watchdog timeout period as a number of 1 kHz ULP oscillator cycles.
In window mode operation, these bits define the open window period. The different typical time-
out periods are found in
Timeout Period (WDP) fuses, and will be loaded at power-on.
In order to change these bits the CEN bit must be written to 1 at the same time. These bits are
protected by the Configuration Change Protection mechanism, for detailed description refer to
”Configuration Change Protection” on page
Table 9-1.
Bit
+0x00
Read/Write
(unlocked)
Read/Write
(locked)
Initial Value
(x = fuse)
PER[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Watchdog timeout periods
R
R
7
–
0
R
R
6
–
0
Table
Group Configuration
R/W
9-1. The initial values of these bits are set by the Watchdog
R
X
5
125CLK
250CLK
500CLK
1KCLK
2KCLK
4KCLK
8KCLK
16CLK
32CLK
64CLK
8CLK
R/W
R
4
X
12.
PER[3:0]
R/W
R
X
3
R/W
R
2
X
Typical timeout periods
ENABLE
R/W
R
X
1
Reserved
Reserved
Reserved
Reserved
Reserved
0.125 s
16 ms
32 ms
64 ms
0.25 s
8 ms
0.5 s
1.0 s
2.0 s
4.0 s
8.0 s
XMEGA D
CEN
R/W
R
0
0
CTRL
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