ATxmega32D4 Atmel Corporation, ATxmega32D4 Datasheet - Page 260
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ATxmega32D4
Manufacturer Part Number
ATxmega32D4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega32D4
Flash (kbytes)
32 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
4
Twi (i2c)
2
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
14
Input Capture Channels
14
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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22.3.2
22.3.3
8210B–AVR–04/10
Disabling
Frame Format and Characters
(refer to device datasheet for external reset pulse width data). This will disable the RESET func-
tionality of the Reset pin, if not already disabled by the fuse settings.
In the next step of the enabling procedure the PDI_DATA line must be kept high for 16 PDI_CLK
cycles (16 positive edges detected). The first PDI_CLK cycle must start no later than 100uS
after the RESET functionality of the Reset pin was disabled. If this does not occur in time the
RESET functionality of the Reset pin is automatically enabled again and the enabling procedure
must start over again.
After this the PDI is enabled and ready to receive instructions. The enable sequence is shown in
Figure 22-3 on page
From the PDI_DATA line goes high and until the first PDI_CLK start, the
The PDI_DATA pin has en internal pull-down resistor that is enabled when the PDI is enabled.
Figure 22-3. Sequence for enabling the PDI.
If the clock frequency on the PDI_CLK is lower than approximately 10 kHz, this is regarding as
inactivity on the clock line. This will then automatically disable the PDI. If not disabled by fuse,
the RESET function on the Reset (PDI_CLK) pin is automatically enabled again. If the time-out
occurs during the PDI enabling sequence, the whole sequence must be started from the
beginning.
This also means that the minimum programming frequency is approximately 10 kHz.
The PDI physical layer uses a fixed frame format. A serial frame is defined to be one character
of eight data bits with start and stop bits and a parity bit.
Figure 22-4. PDI serial frame format.
Table 1.
St
(0-7)
P
Sp1
Sp2
PDI_DATA
PDI_CLK
(IDLE)
Start bit, always low.
Data bits (0 to 7)
Parity bit, even parity is used
Stop bit 1, always high.
Stop bit 2, always high.
St
Disable RESET function on Reset (PDI_CLK) pin
260.
0
1
2
3
4
FRAME
5
6
7
P
Sp1
Activate PDI
Sp2
XMEGA D
(St/IDLE)
260