ATxmega32D4 Atmel Corporation, ATxmega32D4 Datasheet - Page 59
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ATxmega32D4
Manufacturer Part Number
ATxmega32D4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega32D4
Flash (kbytes)
32 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
4
Twi (i2c)
2
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
14
Input Capture Channels
14
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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Company
Part Number
Manufacturer
Quantity
Price
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Part Number:
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Part Number:
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Part Number:
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6.5
Figure 6-5.
8210B–AVR–04/10
External Oscillator or Clock.
Internal 32.768 kHz Osc.
Internal 32 MHz Osc.
Internal 2 MHz Osc.
System Clock Selection and Prescalers
Internal PLL.
System Clock Selection and Prescalers
Clock Selection
6-4 on page
oscillator can be used as clock source for the System Clock, RTC and as the DFLL reference.
Figure 6-4.
Two capacitors, C1 and C2, may be added to match the required load capacitance for the con-
nected crystal.
All the calibrated internal oscillators, the external clock sources (XOSC) and the PLL output can
be used as the System Clock source. The System Clock source is selectable from software, and
can be changed during normal operation. Built-in hardware protection prevents unsafe clock
switching. It is not possible to select a non-stable or disabled oscillator as clock source, or to dis-
able the oscillator currently used as system clock source. Each oscillator option has a status flag
that can be read from software to check that the oscillator is ready.
The System Clock is fed into a prescaler block that can divide the clock signal by a factor from 1
to 2048 before it is routed to the CPU and peripherals. The prescaler settings can be changed
from software during normal operation. The first stage, prescaler A, can divide by a factor of 1 to
512. Then prescaler B and C can be individually configured to either pass the clock through or
divide it by a factor of 1 to 4. The prescaler guarantees that derived clocks are always in phase,
and that no glitches or intermediate frequencies occur when changing the prescaler setting. The
prescaler settings are always updated in accordance to the rising edge of the slowest clock.
Prescaler A divides the System Clock and the resulting clock is the clk
prescaler C can be enabled to divide the clock speed further and enable peripheral modules to
run at twice or four times the CPU Clock frequency. If Prescaler B and C are not used all the
clocks will run at the same frequency as output from Prescaler A.
Clk
SYS
1, 2, 4, ... , 512
Prescaler A
59. A low power mode with reduced voltage swing on TOSC2 is available. This
32.768 kHz crystal oscillator connection
Clk
Prescaler B
PER4
1, 2, 4
C 2
C 1
Clk
Prescaler C
PER2
1, 2
T O S C 2
T O S C 1
G N D
Clk
Clk
CPU
PER
PER4
XMEGA D
. Prescaler B and
59