ATxmega32D4 Atmel Corporation, ATxmega32D4 Datasheet - Page 117
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ATxmega32D4
Manufacturer Part Number
ATxmega32D4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega32D4
Flash (kbytes)
32 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
4
Twi (i2c)
2
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
14
Input Capture Channels
14
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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8210B–AVR–04/10
• Bit 7:6 - Reserved
These bits are reserved and will always be read as one. For compatibility with future devices,
always write these bits to zero when this register is written.
• Bit 5:4 - EVOUT[1:0] - Event Output Port
These bits decide which port the Event Channel 0 from the Event System should be output to.
Pin 7 on the selected port is always used, and the CLKOUT bits must be set different from
EVOUT. The pin must be configured as an output pin for the Signaling Event to be available on
the pin.
Table 11-7 on page 117
Table 11-7.
• Bits 3:2 - CLKOUTSEL[1:0] - Clock Output Select
These bits are used to select which clock is output to pin.
Table 11-8.
• Bit 1:0 - CLKOUT[1:0] - Clock Output Port
These bits decide which port the Peripheral Clock should be output to. Pin 7 on the selected port
is always used. The Clock output setting, will override the Event output setting, thus if both are
enabled on the same port pin, the Peripheral Clock will be visible. The pin must be configured as
an output pin for the Clock to be available on the pin.
Table 11-9 on page 117
Table 11-9.
EVOUT[1:0]
00
01
10
11
CLKOUTSEL[1:0]
00
01
10
CLKOUT[1:0]
00
01
10
11
Event Channel 0 output configurations
Clock Output Select
Clock output configurations
shows the possible configurations.
shows the possible configurations.
Group Configuration
OFF
PC7
PD7
PE7
Group Configuration
CLK1X
CLK2X
CLK4X
Group Configuration
OFF
PC7
PD7
PE7
Description
Event out disabled
Event Channel 0 output on Port C pin 7
Event Channel 0 output on Port D pin 7
Event Channel 0 output on Port E pin 7
Description
CLK
CLK
CLK
Description
Clock out disabled
Clock output on Port C pin 7
Clock output on Port D pin 7
Clock output on Port E pin 7
PER
PER2
PER4
output to pin
output to pin
output to pin
XMEGA D
117