ATxmega32D4 Atmel Corporation, ATxmega32D4 Datasheet - Page 208
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ATxmega32D4
Manufacturer Part Number
ATxmega32D4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega32D4
Flash (kbytes)
32 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
4
Twi (i2c)
2
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
14
Input Capture Channels
14
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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Price
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18.8.2
18.8.3
8210B–AVR–04/10
Asynchronous Data Recovery
Asynchronous Operational Range
The data recovery unit uses sixteen samples in Normal mode and eight samples in Double
Speed mode for each bit.
ity bits.
Figure 18-7. Sampling of Data and Parity Bit
As for start bit detection, identical majority voting technique is used on the three center samples
(indicated with sample numbers inside boxes) for deciding of the logic level of the received bit.
This majority voting process acts as a low pass filter for the received signal on the RxD pin. The
process is repeated for each bit until a complete frame is received. Including the first, but exclud-
ing additional stop bits. If the stop bit sampled has a logic 0 value, the Frame Error (FERR) Flag
will be set.
Figure 18-8 on page 208
beginning of the next frame's start bit.
Figure 18-8. Stop Bit Sampling and Next Start Bit Sampling
A new high to low transition indicating the start bit of a new frame can come right after the last of
the bits used for majority voting. For Normal Speed mode, the first low level sample can be at
point marked (A) in Stop Bit Sampling and Next Start Bit Sampling. For Double Speed mode the
first low level must be delayed to (B). (C) marks a stop bit of full length at nominal baud rate. The
early start bit detection influences the operational range of the Receiver.
The operational range of the Receiver is dependent on the mismatch between the received bit
rate and the internally generated baud rate. If an external Transmitter is sending on bit rates that
are too fast or too slow, or the internally generated baud rate of the Receiver does not match the
external source’s base frequency, the Receiver will not be able to synchronize the frames to the
start bit.
(CLK2X = 0)
(CLK2X = 1)
(CLK2X = 0)
(CLK2X = 1)
Sample
Sample
Sample
Sample
RxD
RxD
1
1
1
1
Figure 18-7 on page 208
2
2
shows the sampling of the stop bit in relation to the earliest possible
3
2
3
2
4
4
5
3
5
3
6
6
7
4
7
4
8
8
STOP 1
shows the sampling process of data and par-
BIT n
9
5
9
5
10
10
(A)
0/1
11
6
6
0/1
12
(B)
0/1
0/1
13
7
14
15
8
XMEGA D
16
(C)
1
1
208