ATxmega32D4 Atmel Corporation, ATxmega32D4 Datasheet - Page 186
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ATxmega32D4
Manufacturer Part Number
ATxmega32D4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega32D4
Flash (kbytes)
32 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
4
Twi (i2c)
2
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
14
Input Capture Channels
14
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega32D4-AU
Manufacturer:
Atmel
Quantity:
123
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Manufacturer:
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Quantity:
20 000
Company:
Part Number:
ATxmega32D4-CU
Manufacturer:
Maxim
Quantity:
71
Company:
Part Number:
ATxmega32D4-MH
Manufacturer:
Atmel
Quantity:
1 910
Company:
Part Number:
ATxmega32D4-MH
Manufacturer:
Atmel
Quantity:
1 704
Part Number:
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Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
16.9.6
16.9.7
8210B–AVR–04/10
ADDR - TWI Master Address Register
DATA -TWI Master Data Register
When the Address (ADDR) register is written with a slave address and the R/W-bit while the bus
is idle, a START condition is issued, and the 7-bit slave address and the R/W-bit are transmitted
on the bus. If the bus is already owned when ADDR is written, a Repeated START is issued. If
the previous transaction was a Master Read and no acknowledge is sent yet, the Acknowledge
Action is sent before the Repeated START condition.
After completing the operation and the acknowledge bit from the slave is received, the SCL line
is forced low if arbitration was not lost. The WIF is set.
If the Bus State is unknown when ADDR is written. The WIF is set, and the BUSERR flag is set.
All TWI master flags are automatically cleared when ADDR is written. This includes BUSERR,
ARBLOST, RIF, and WIF. The Master ADDR can be read at any time without interfering with
ongoing bus activity.
The data (DATA) register is used when transmitting and receiving data. During data transfer,
data is shifted from/to the DATA register and to/from the bus. This implies that the DATA register
cannot be accessed during byte transfers, and this is protected in hardware. The Data register
can only be accessed when the SCL line is held low by the master, i.e. when CLKHOLD is set.
In Master Write mode, writing the DATA register will trigger a data byte transfer, followed by the
master receiving the acknowledge bit from the slave. The WIF and the CLKHOLD flag are set.
In Master Read mode the RIF and the CLKHOLD flag are set when one byte is received in the
DATA register. If Smart Mode is enabled, reading the DATA register will trigger the bus opera-
tion as set by the ACKACT bit. If a bus error occurs during reception the WIF and BUSERR flag
are set instead of the RIF.
Accessing the DATA register will clear the master interrupt flags and the CLKHOLD flag.
Bit
+0x05
Read/Write
Initial Value
Bit
+0x05
Read/Write
Initial Value
R/W
R/W
7
0
7
0
R/W
R/W
6
0
6
0
R/W
R/W
5
0
5
0
R/W
R/W
4
0
4
0
ADDR[7:0]
DATA[7:0]
R/W
R/W
3
0
3
0
R/W
R/W
2
0
2
0
R/W
R/W
1
0
1
0
XMEGA D
R/W
R/W
0
0
0
0
ADDR
DATA
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