876784 Intel, 876784 Datasheet - Page 767

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

Serial Peripheral Interface (SPI) (Desktop and Mobile Only)
21.1.1
Intel
®
ICH7 Family Datasheet
SPIS—SPI Status Register
(SPI Memory Mapped Configuration Registers)
Memory Address:SPIBAR + 00h
Default Value:
14:4
Bit
15
3
2
1
0
SPI Configuration Lock-Down — R/WLO.
0 = No Lock-Down (Default)
1 = SPI Static Configuration information in offsets 50h through 6Fh can not be
Reserved
Blocked Access Status — R/WC.
0 = Not blocked (Default)
1 = Hardware sets this bit to 1 when an access is blocked from running on the SPI
NOTE: This bit remains asserted until cleared by software writing a 1 or hardware
Cycle Done Status— R/WC.
0 = Not done (Default)
1 = The Intel
NOTE: This bit remains asserted until cleared by software writing a 1 or hardware
NOTE: Software must make sure this bit is cleared prior to enabling the SPI SMI#
NOTE: This bit gets set after the Status Register Polling sequence completes after reset
SPI Access Grant — RO. This bit is used by the software to know when the other SPI
master will not be initiating any long transactions on the SPI bus.
0 = Default
1 = It is set by hardware in response to software setting the SPI Access Request bit and
NOTE: This bit is cleared in response to software clearing the SPI Access Request bit.
SPI Cycle In Progress (SCIP) — RO.
0 = Cycle Not in Progress (Default)
1 = Hardware sets this bit when software sets the SPI Cycle Go bit in the Command
This bit reports 1b during the Status Register Polling sequence after reset deasserts; it
is cleared when that sequence completes.
NOTE: Software must only program the next command when this bit is 0.
overwritten. Once set to 1, this bit can only be cleared by a hardware reset.
interface due to one of the protection policies or when any of the programmed cycle
registers is written while a programmed access is already in progress. This bit is set
for both programmed accesses and direct memory reads that get blocked.
after software sets the SCGO bit.
completing the Future Pending handshake with the LAN component.
register. This bit remains set until the cycle completes on the SPI interface.
Hardware automatically sets and clears this bit so that software can determine
when read data is valid and/or when it is safe to begin programming the next
command.
reset.
reset.
assertion for a new programmed access.
deasserts. It is cleared before and during that sequence.
See bit description
®
ICH7 sets this bit to 1 when the SPI Cycle completes (i.e., SCIP bit is 0)
Description
Attribute:
Size:
RO, R/WC, R/WLO
16 bits
767