876784 Intel, 876784 Datasheet - Page 440

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

10.8.3.9
10.8.3.10
440
PM2_CNT—Power Management 2 Control Register (Mobile/Ultra
Mobile Only)
I/O Address:
Default Value:
Lockable:
Power Well:
GPE0_STS—General Purpose Event 0 Status Register
I/O Address:
Default Value:
Lockable:
Power Well:
This register is symmetrical to the General Purpose Event 0 Enable Register. Unless
indicated otherwise below, if the corresponding _EN bit is set, then when the _STS bit
get set, the ICH7 will generate a Wake Event. Once back in an S0 state (or if already in
an S0 state when the event occurs), the ICH7 will also generate an SCI if the SCI_EN
bit is set, or an SMI# if the SCI_EN bit (PMBASE + 04h, bit 0) is not set. Bits 31:16 are
reset by a CF9h write; bits 15:0 are not. All are reset by RSMRST#.
7:1
Bit
31:16
0
Bit
15
14
Reserved
Arbiter Disable (ARB_DIS) — R/W. This bit is a scratchpad bit for legacy software
compatibility. Software typically sets this bit to 1 prior to entering a C3 or C4 state.
When a transition to a C3 or C4 state occurs, Intel
prevent any internal or external non-Isoch bus masters from initiating any cycles up to
the (G)MCH. This blocking starts immediately upon the ICH7 sending the Go–C3
message to the (G)MCH. The blocking stops when the Ack-C2 message is received.
Note that this is not really blocking, in that messages (such as from PCI Express*) are
just queued and held pending.
GPIOn_STS — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = These bits are set any time the corresponding GPIO is set up as an input and the
NOTE: Mapping is as follows: bit 31 corresponds to GPIO15 ... and bit 16
Reserved
USB4_STS — R/WC.
0 = Disable.
1 = Set by hardware and can be reset by writing a one to this bit position or a
• If the system is in an S1–S5 state, the event will also wake the system.
• If the system is in an S0 state (or upon waking back to an S0 state), a SCI will be caused
depending on the GPIO_ROUT bits (D31:F0:B8h, bits 31:30) for the corresponding GPI.
corresponding GPIO signal is high (or low if the corresponding GP_INV bit is set).
If the corresponding enable bit is set in the GPE0_EN register, then when the
GPIO[n]_STS bit is set:
resume well reset. This bit is set when USB UHCI controller #4 needs to cause a
wake. Additionally if the USB4_EN bit is set, the setting of the USB4_STS bit will
generate a wake event.
PMBASE + 20h
(ACPI PM2_BLK)
00h
No
Core
PMBASE + 28h
(ACPI GPE0_BLK)
00000000h
No
Resume
corresponds to GPIO0.
Description
Description
Attribute:
Size:
Usage:
Attribute:
Size:
Usage:
LPC Interface Bridge Registers (D31:F0)
®
ICH7-M/ICH7-U will automatically
Intel
R/W
8-bit
ACPI
R/WC
32-bit
ACPI
®
ICH7 Family Datasheet