876784 Intel, 876784 Datasheet - Page 435

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

LPC Interface Bridge Registers (D31:F0)
10.8.3.2
Intel
®
ICH7 Family Datasheet
PM1_EN—Power Management 1 Enable Register
I/O Address:
Default Value:
Lockable:
Power Well:
(Desktop
Mobile
Mobile
13:11
(Ultra
Only)
Only)
and
7:6
4:1
Bit
15
14
14
10
9
8
5
0
Reserved
PCI Express Wake Disable(PCIEXPWAK_DIS) — R/W. Modification of this bit
has no impact on the value of the PCIEXP_WAKE_STS bit.
0 = Inputs to the PCIEXP_WAKE_STS bit in the PM1 Status register enabled to wake
1 = Inputs to the PCIEXP_WAKE_STS bit in the PM1 Status register disabled from
Reserved
Reserved
RTC Event Enable (RTC_EN) — R/W. This bit is in the RTC well to allow an RTC
event to wake after a power failure. This bit is not cleared by any reset other than
RTCRST# or a Power Button Override event.
0 = No SCI (or SMI#) or wake event is generated then RTC_STS (PMBASE + 00h, bit
1 = An SCI (or SMI#) or wake event will occur when this bit is set and the RTC_STS
Reserved.
Power Button Enable (PWRBTN_EN) — R/W. This bit is used to enable the
setting of the PWRBTN_STS bit to generate a power management event (SMI#,
SCI). PWRBTN_EN has no effect on the PWRBTN_STS bit (PMBASE + 00h, bit 8)
being set by the assertion of the power button. The Power Button is always enabled
as a Wake event.
0 = Disable.
1 = Enable.
Reserved.
Global Enable (GBL_EN) — R/W. When both the GBL_EN and the GBL_STS bit
(PMBASE + 00h, bit 5) are set, an SCI is raised.
0 = Disable.
1 = Enable SCI on GBL_STS going active.
Reserved.
Timer Overflow Interrupt Enable (TMROF_EN) — R/W. Works in conjunction
with the SCI_EN bit (PMBASE + 04h, bit 0) as described below:
TMROF_EN
the system.
waking the system.
10) goes active.
bit goes active.
PMBASE + 02h
(ACPI PM1a_EVT_BLK + 2) Attribute:
0000h
No
Bits 0
Bits 8
Bit 10: RTC
0
1
1
–
–
7: Core,
9, 11
–
SCI_EN
15: Resume,
X
0
1
Effect when TMROF_STS is set
Description
Size:
Usage:
No SMI# or SCI
SMI#
SCI
R/W
16-bit
ACPI or Legacy
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