876784 Intel, 876784 Datasheet - Page 222

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

Note:
Note:
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The block write begins with a slave address and a write condition. After the command
code the ICH7 issues a byte count describing how many more bytes will follow in the
message. If a slave had 20 bytes to send, the first byte would be the number 20 (14h),
followed by 20 bytes of data. The byte count may not be 0. A Block Read or Write is
allowed to transfer a maximum of 32 data bytes.
When programmed for a block write command, the Transmit Slave Address, Device
Command, and Data0 (count) registers are sent. Data is then sent from the Block Data
Byte register; the total data sent being the value stored in the Data0 Register. On block
read commands, the first byte received is stored in the Data0 register, and the
remaining bytes are stored in the Block Data Byte register. See section 5.5.7 of the
System Management Bus (SMBus) Specification, Version 2.0 for the format of the
protocol.
For Block Write, if the I2C_EN bit is set, the format of the command changes slightly.
The ICH7 will still send the number of bytes (on writes) or receive the number of bytes
(on reads) indicated in the DATA0 register. However, it will not send the contents of the
DATA0 register as part of the message. Also, the Block Write protocol sequence
changes slightly: the Byte Count (bits 27:20 in the bit sequence) are not sent - as a
result, the slave will not acknowledge (bit 28 in the sequence).
I
This command allows the ICH7 to perform block reads to certain I
serial E
However, this does not allow access to devices using the I
has data bytes after the address. Typically these data bytes correspond to an offset
(address) within the serial memory chips.
This command is supported independent of the setting of the I2C_EN bit. The I
command with the PEC_EN bit set produces undefined results. Software must force
both the PEC_EN and AAC bit to 0 when running this command.
For I
Register (SMB I/O register, offset 04h) needs to be 0.
2
C Read
2
C Read command, the value written into bit 0 of the Transmit Slave Address
2
PROMs. The SMBus Block Read supports the 7-bit addressing mode only.
2
C “Combined Format” that
Intel
®
2
C devices, such as
ICH7 Family Datasheet
Functional Description
2
C Read