876784 Intel, 876784 Datasheet - Page 466

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

10.10.5
10.10.6
466
GPI_INV—GPIO Signal Invert Register
Offset Address: GPIOBASE +2Ch
Default Value:
Lockable:
GPIO_USE_SEL2—GPIO Use Select 2 Register[63:32]
Offset Address: GPIOBASE +30h
Default Value:
Lockable:
17:16,
31:0
Bit
7:0
Bit
GP_INV[n] — R/W. Input Inversion: This bit only has effect if the corresponding
GPIO is used as an input and used by the GPE logic, where the polarity matters. When
set to 1, then the GPI is inverted as it is sent to the GPE logic that is using it. This bit
has no effect on the value that is reported in the GP_LVL register.
These bits are used to allow both active-low and active-high inputs to cause SMI# or
SCI. Note that in the S0 or S1 state, the input signal must be active for at least two PCI
clocks to ensure detection by the Intel
signal must be active for at least 2 RTC clocks to ensure detection. The setting of these
bits has no effect if the corresponding GPIO is programmed as an output. These bits
correspond to GPI that are in the resume well, and will be reset to their default values
by RSMRST# or by a write to the CF9h register.
0 = The corresponding GPI_STS bit is set when the ICH7 detects the state of the input
1 = The corresponding GPI_STS bit is set when the ICH7 detects the state of the input
GPIO_USE_SEL2[49:48, 39:32] Bits[17:16, 7:0]— R/W. Each bit in this register
enables the corresponding GPIO (if it exists) to be used as a GPIO, rather than for the
native function.
0 = Signal used as native function.
1 = Signal used as a GPIO.
After a full reset (RSMRST#), all multiplexed signals in the resume and core wells are
configured as a GPIO rather than as their native function. After just a PLTRST#, the
GPIO in the core well are configured as GPIO.
NOTES:
1.
2.
pin to be high.
pin to be low.
The following bits are not implemented because there is no corresponding
GPIO: 31:18, 15:8.
The following bits are not implemented because they are determined by the
Desktop/Mobile/Ultra Mobile configuration: 0
00000000h
No
000300FFh (Desktop Only)
000300FEh (Mobile/Ultra Mobile Only)
No
Description
Description
®
ICH7. In the S3, S4 or S5 states the input
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
LPC Interface Bridge Registers (D31:F0)
Intel
R/W
32-bit
Core for 0:7, 16:23,
Resume for 8:15, 24:31
R/W
32-bit
CPU I/O for 17, Core for
16, 7:0
®
ICH7 Family Datasheet