876784 Intel, 876784 Datasheet - Page 426

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

10.8.1.6
426
BM_BREAK_EN Register (PM—D31:F0) (Mobile/Ultra Mobile Only)
Offset Address: ABh
Default Value:
Lockable:
Power Well:
(Mobile
Mobile
(Ultra
Only)
Only)
4:3
Bit
7
6
6
5
2
1
0
IDE_BREAK_EN — R/W.
0 = Parallel IDE or Serial ATA traffic will not act as a break event.
1 = Parallel IDE or Serial ATA traffic acts as a break event, even if the BM_STS-
PCIE_BREAK_EN — R/W.
0 = PCI Express* traffic will not act as a break event.
1 = PCI Express traffic acts as a break event, even if the BM_STS-ZERO_EN and
Reserved
PCI_BREAK_EN — R/W.
0 = PCI traffic will not act as a break event.
1 = PCI traffic acts as a break event, even if the BM_STS-ZERO_EN and POPUP_EN
Reserved
EHCI_BREAK_EN — R/W.
0 = EHCI traffic will not act as a break event.
1 = EHCI traffic acts as a break event, even if the BM_STS-ZERO_EN and POPUP_EN
UHCI_BREAK_EN — R/W.
0 = UHCI traffic will not act as a break event.
1 = USB traffic from any of the internal UHCIs acts as a break event, even if the
ACAZ_BREAK_EN — R/W.
0 = AC ‘97 or Intel
1 = AC ‘97 or Intel High Definition Audio traffic acts as a break event, even if the
NOTE: For ICH7-U Ultra Mobile, only Intel High Definition is supported, AC ‘97 is not
ZERO_EN and POPUP_EN bits are set. Parallel IDE or Serial ATA master activity
will cause BM_STS to be set and will cause a break from C3/C4.
POPUP_EN bits are set. PCI Express master activity will cause BM_STS to be set
and will cause a break from C3/C4.
bits are set. PCI master activity will cause BM_STS to be set and will cause a
break from C3/C4.
bits are set. EHCI master activity will cause BM_STS to be set and will cause a
break from C3/C4.
BM_STS-ZERO_EN and POPUP_EN bits are set. UHCI master activity will cause
BM_STS to be set and will cause a break from C3/C4.
BM_STS-ZERO_EN and POPUP_EN bits are set. AC ‘97 or Intel High Definition
Audio master activity will cause BM_STS to be set and will cause a break from
C3/C4.
00h
No
Core
supported.
®
High Definition Audio traffic will not act as a break event.
Description
Attribute:
Size:
Usage:
LPC Interface Bridge Registers (D31:F0)
Intel
R/W
8-bit
ACPI, Legacy
®
ICH7 Family Datasheet