876784 Intel, 876784 Datasheet - Page 577

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

EHCI Controller Registers (D29:F7)
13.2.3
Table 13-4. Debug Port Register Address Map
13.2.3.1
Intel
®
ICH7 Family Datasheet
USB 2.0-Based Debug Port Register
The Debug port’s registers are located in the same memory area, defined by the Base
Address Register (MEM_BASE), as the standard EHCI registers. The base offset for the
debug port registers (A0h) is declared in the Debug Port Base Offset Capability Register
at Configuration offset 5Ah (D29:F7:offset 5Ah). The specific EHCI port that supports
this debug capability (port 0) is indicated by a 4-bit field (bits 20
HCSPARAMS register of the EHCI controller. The address map of the Debug Port
registers is shown in
NOTES:
1.
2.
CNTL_STS—Control/Status Register
Offset:
Default Value:
MEM_BASE +
27:17
Bit
31
30
29
28
A0–A3h
A4–A7h
A8–ABh
AC–AFh
B0–B3h
Offset
All of these registers are implemented in the core well and reset by PLTRST#, EHC
HCRESET, and a EHC D3-to-D0 transition
The hardware associated with this register provides no checks to ensure that software
programs the interface correctly. How the hardware behaves when programmed
inappropriately is undefined.
Reserved
OWNER_CNT — R/W.
0 = Ownership of the debug port is NOT forced to the EHCI controller (Default)
1 = Ownership of the debug port is forced to the EHCI controller (i.e. immediately
Reserved
ENABLED_CNT — R/W.
0 = Software can clear this by writing a 0 to it. The hardware clears this bit for the
1 = Debug port is enabled for operation. Software can directly set this bit if the port is
Reserved
taken away from the companion Classic USB Host controller) If the port was
already owned by the EHCI controller, then setting this bit has no effect. This bit
overrides all of the ownership-related bits in the standard EHCI registers.
same conditions where the Port Enable/Disable Change bit (in the PORTSC
register) is set. (Default)
already enabled in the associated PORTSC register (this is enforced by the
hardware).
DATABUF[3:0]
DATABUF[7:4]
Mnemonic
MEM_BASE + A0h
0000h
CNTL_STS
USBPID
CONFIG
Table
13-4.
Control/Status
Data Buffer (Bytes 7:4)
Configuration
USB PIDs
Data Buffer (Bytes 3:0)
Register Name
Description
.
Attribute:
Size:
00000000h
00000000h R/W, RO
00000000h R/W
00000000h R/W
00007F01h
Default
R/W, R/WC, RO, WO
32 bits
–
23) in the
R/W, R/WC, RO,
WO
R/W
Type
577