876784 Intel, 876784 Datasheet - Page 133

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

Functional Description
5.9
.
Table 5-13. Interrupt Controller Core Connections
Intel
®
ICH7 Family Datasheet
Both count and status of the selected counters may be latched simultaneously. This is
functionally the same as issuing two consecutive, separate Read Back commands. If
multiple count and/or status Read Back commands are issued to the same counters
without any intervening reads, all but the first are ignored.
If both count and status of a counter are latched, the first read operation from that
counter returns the latched status, regardless of which was latched first. The next one
or two reads, depending on whether the counter is programmed for one or two type
counts, returns the latched count. Subsequent reads return unlatched count.
8259 Interrupt Controllers (PIC) (D31:F0)
The ICH7 incorporates the functionality of two 8259 interrupt controllers that provide
system interrupts for the ISA compatible interrupts. These interrupts are: system
timer, keyboard controller, serial ports, parallel ports, floppy disk, IDE, mouse, and
DMA channels. In addition, this interrupt controller can support the PCI based
interrupts, by mapping the PCI interrupt onto the compatible ISA interrupt line. Each
8259 core supports eight interrupts, numbered 0
are connected.
The ICH7 cascades the slave controller onto the master controller through master
controller interrupt input 2. This means there are only 15 possible interrupts for the
ICH7 PIC.
Master
8259
Slave
Input
8259
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Internal
Keyboard
Internal
Serial Port A
Serial Port B
Parallel Port / Generic
Floppy Disk
Parallel Port / Generic
Internal Real Time
Clock
Generic
Generic
Generic
PS/2 Mouse
Internal
IDE cable, SATA
IDE cable, SATA
Typical Interrupt
Source
Internal Timer / Counter 0 output / HPET #0
IRQ1 via SERIRQ
Slave controller INTR output
IRQ3 via SERIRQ, PIRQ#
IRQ4 via SERIRQ, PIRQ#
IRQ5 via SERIRQ, PIRQ#
IRQ6 via SERIRQ, PIRQ#
IRQ7 via SERIRQ, PIRQ#
Internal RTC / HPET #1
IRQ9 via SERIRQ, SCI, TCO, or PIRQ#
IRQ10 via SERIRQ, SCI, TCO, or PIRQ#
IRQ11 via SERIRQ, SCI, TCO, or PIRQ#
IRQ12 via SERIRQ, SCI, TCO, or PIRQ#
State Machine output based on processor FERR#
assertion. May optionally be used for SCI or TCO
interrupt if FERR# not needed.
IDEIRQ (legacy mode, non-combined or combined
mapped as primary), SATA Primary (legacy mode),
or via SERIRQ or PIRQ#
IDEIRQ (legacy mode — combined, mapped as
secondary), SATA Secondary (legacy mode) or via
SERIRQ or PIRQ#
–
7.
Connected Pin / Function
Table 5-13
shows how the cores
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