876784 Intel, 876784 Datasheet - Page 104
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876784
Manufacturer Part Number
876784
Description
Manufacturer
Intel
Datasheet
1.876784.pdf
(848 pages)
Specifications of 876784
Lead Free Status / RoHS Status
Compliant
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Table 5-3.
5.2.2
5.2.2.1
5.2.2.2
5.2.2.3
104
MSI vs. PCI IRQ Actions
Power Management
S3/S4/S5 Support
Software initiates the transition to S3/S4/S5 by performing an IO write to the Power
Management Control register in the ICH7. After the IO write completion has been
returned to the processor, each root port will send a PME_Turn_Off TLP (Transaction
Layer Packet) message on it's downstream link. The device attached to the link will
eventually respond with a PME_TO_Ack TLP message followed by sending a
PM_Enter_L23 DLLP (Data Link Layer Packet) request to enter the L2/L3 Ready state.
When all of the ICH7 root ports links are in the L2/L3 Ready state, the ICH7 power
management control logic will proceed with the entry into S3/S4/S5.
Prior to entering S3, software is required to put each device into D3
is put into D3
DLLP. Thus, under normal operating conditions when the root ports sends the
PME_Turn_Off message, the link will be in state L1. However, when the root port is
instructed to send the PME_Turn_Off message, it will send it whether or not the link
was in L1. Endpoints attached to the ICH7 can make no assumptions about the state of
the link prior to receiving a PME_Turn_Off message.
Resuming from Suspended State
The root port contains enough circuitry in the resume well to detect a wake event thru
the WAKE# signal and to wake the system. When WAKE# is detected asserted, an
internal signal is sent to the power management controller of the ICH7 to cause the
system to wake up. This internal message is not logged in any register, nor is an
interrupt/GPE generated due to it.
Device Initiated PM_PME Message
When the system has returned to a working state from a previous low power state, a
device requesting service will send a PM_PME message continuously, until acknowledge
by the root port. The root port will take different actions depending upon whether this
is the first PM_PME has been received, or whether a previous message has been
received but not yet serviced by the operating system.
If this is the first message received (RSTS.PS - D28:F0/F1/F2/F3/F4/F5:Offset 60h:bit
16 is cleared), the root port will set RSTS.PS, and log the PME Requester ID into
RSTS.RID (D28:F0/F1/F2/F3/F4/F5:Offset 60h:bits 15:0). If an interrupt is enabled via
All bits 0
One or more bits set to 1
One or more bits set to 1, new bit gets set to 1
One or more bits set to 1, software clears some (but not all)
bits
One or more bits set to 1, software clears all bits
Software clears one or more bits, and one or more bits are
set on the same clock
HOT
, it will initiate entry into a L1 link state by sending a PM_Enter_L1
Interrupt Register
Mode Action
Wire inactive
Wire inactive
Wire active
Wire active
Wire active
Wire active
Intel
Wire-
®
ICH7 Family Datasheet
HOT
Functional Description
. When a device
MSI Action
No action
No action
message
message
message
message
Send
Send
Send
Send
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