876784 Intel, 876784 Datasheet - Page 662

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

17.2.9
662
GLOB_STA—Global Status Register (Modem—D30:F3)
I/O Address:
Default Value:
Lockable:
31:30
23:22
21:20
19:18
Bit
29
28
27
26
25
24
17
16
Reserved.
ACZ_SDIN2 Resume Interrupt (S2RI)
occurred on ACZ_SDIN2.
0 = Software clears this bit by writing a 1 to it.
1 = Resume event occurred.
NOTE: This bit is not affected by D3
ACZ_SDIN2 Codec Ready (S2CR)
ready bit on ACZ_SDIN2. Bus masters ignore the condition of the codec ready bits, so
software must check this bit before starting the bus masters. Once the codec is “ready”,
it must not go “not ready” spontaneously.
0 = Not Ready.
1 = Ready.
Bit Clock Stopped (BCS)
0 = Transition is found on BIT_CLK.
1 = Intel
S/PDIF* Interrupt (SPINT)
0 = When the specific status bit is cleared, this bit will be cleared.
1 = S/PDIF out channel interrupt status bits have been set.
PCM In 2 Interrupt (P2INT)
0 = When the specific status bit is cleared, this bit will be cleared.
1 = One of the PCM In 2 channel status bits have been set.
Microphone 2 In Interrupt (M2INT)
0 = When the specific status bit is cleared, this bit will be cleared.
1 = One of the Mic in channel interrupts status bits has been set.
Sample Capabilities
16-bit audio.
00 = Reserved
01 = 16 and 20-bit Audio supported (ICH7 value)
10 = Reserved
11 = Reserved
Multichannel Capabilities
channels on PCM Out.
Reserved.
MD3 — R/W. Power down semaphore for Modem. This bit exists in the suspend well
and maintains context across power states (except G3). The bit has no hardware
function. It is used by software in conjunction with the AD3 bit to coordinate the entry
of the two codecs into D3 state.
NOTE: This bit is not affected by D3
AD3 — R/W. Power down semaphore for Audio. This bit exists in the suspend well and
maintains context across power states (except G3). The bit has no hardware function.
It is used by software in conjunction with the MD3 bit to coordinate the entry of the two
codecs into D3 state.
NOTE: This bit is not affected by D3
consecutive PCI clocks.
®
MBAR + 40h
00300000h
No
ICH7 detects that there has been no transition on BIT_CLK for four
AC ’97 Modem Controller Registers (D30:F3) (Desktop and Mobile Only)
—
RO. This field indicates the capability to support greater than
—
—
RO. This bit indicates that the bit clock is not running.
—
RO. This field indicates the capability to support 4 and 6
—
RO.
RO.
HOT
HOT
HOT
—
Description
—
to D0 Reset.
RO. This bit reflects the state of the codec
to D0 Reset.
to D0 Reset.
Attribute:
Size:
Power Well:
—
RO.
R/WC. This bit indicates a resume event
Intel
RO, R/W, R/WC
32 bits
Core
®
ICH7 Family Datasheet