876784 Intel, 876784 Datasheet - Page 160

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

Table 5-29. Break Events (Mobile/Ultra Mobile Only)
5.14.5.1
160
Transition Rules among S0/Cx and Throttling States
The following priority rules and assumptions apply among the various S0/Cx and
throttling states:
Any unmasked interrupt goes
active
Any internal event that cause an
NMI or SMI#
Any internal event that cause
INIT# to go active
Any bus master request
(internal, external or DMA, or
BM_BUSY#) goes active and
BM_RLD=1 (D31:F0:Offset
PMBASE+04h: bit 1)
Processor Pending Break Event
Indication
• Entry to any S0/Cx state is mutually exclusive with entry to any S1–S5 state. This
• When the SLP_EN bit is set (system going to a S1–S5 sleep state), the THTL_EN
• (Mobile/Ultra Mobile Only) If the THTL_EN or FORCE_THTL bits are set, and a Level
• (Mobile/Ultra Mobile Only) After an exit from a C2, C3, or C4 state (due to a Break
• The Host controller must post Stop-Grant cycles in such a way that the processor
• (Mobile/Ultra Mobile Only) If in the C1 state and the STPCLK# signal goes active,
is because the processor can only perform one register access at a time and Sleep
states have higher priority than thermal throttling.
and FORCE_THTL bits can be internally treated as being disabled (no throttling
while going to sleep state).
2, Level 3, or Level 4 read then occurs, the system should immediately go and stay
in a C2, C3, or C4 state until a break event occurs. A Level 2, Level 3, or Level 4
read has higher priority than the software initiated throttling.
event), and if the THTL_EN or FORCE_THTL bits are still set the system will
continue to throttle STPCLK#. Depending on the time of break event, the first
transition on STPCLK# active can be delayed by up to one THRM period (1024 PCI
clocks = 30.72 µs).
gets an indication of the end of the special cycle prior to the ICH7 observing the
Stop-Grant cycle. This ensures that the STPCLK# signals stays active for a
sufficient period after the processor observes the response phase.
the processor will generate a Stop-Grant cycle, and the system should go to the C2
state. When STPCLK# goes inactive, it should return to the C1 state.
Event
C2, C3, C4
C2, C3, C4
C2, C3, C4
C2, C3, C4
Breaks
C3, C4
from
IRQ[0:15] when using the 8259s, IRQ[0:23]
for I/O APIC. Since SCI is an interrupt, any SCI
will also be a break event.
Many possible sources
Could be indicated by the keyboard controller
via the RCIN input signal.
Need to wake up processor so it can do snoops
NOTE: If the PUME bit (D31:F0: Offset A9h: bit
Only available if FERR# enabled for break event
indication (See FERR# Mux Enable in GCS,
Chipset Config Registers:Offset 3410h:bit 6)
3) is set, then bus master activity will
NOT be treated as a break event.
Instead, there will be a return only to
the C2 state.
Comment
Intel
®
ICH7 Family Datasheet
Functional Description