876784 Intel, 876784 Datasheet - Page 683

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

PCI Express* Configuration Registers (Desktop and Mobile Only)
18.1.29
Intel
®
ICH7 Family Datasheet
LSTS—Link Status Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 52h–53h
Default Value:
15:14
1:0
9:4
3:0
Bit
Bit
13
12
11
10
Active State Link PM Control (APMC) — R/W. This bit indicates whether the root
port should enter L0s or L1 or both.
Reserved
Data Link Layer Active (DLLA) — RO. D
0 = Data Link Control and Management State Machine is not in the DL_Active state.
1 = Data Link Control and Management State Machine is in the DL_Active state.
Slot Clock Configuration (SCC) — RO. Set to 1b to indicate that the Intel
the same reference clock as on the platform and does not generate its own clock.
Link Training (LT) — RO.
0 = Link training completed. (Default)
1 = Link training is occurring.
Link Training Error (LTE) — RO. Not supported. Set value is 0b.
Negotiated Link Width (NLW) — RO. This field indicates the negotiated width of the
given PCI Express* link. The contents of this NLW field is undefined if the link has not
successfully trained.
NOTE: 000001b = x1 link width, 000010b =x2 linkwidth (not supported),
Link Speed (LS) — RO. This field indicates the negotiated Link speed of the given PCI
Express* link.
01h = Link is 2.5 Gb/s.
(Default)
Bits
Port #
00b
01b
10b
11b
1
2
3
4
5
6
000100 = x4 linkwidth
See bit description
Definition
Disabled
L0s Entry is Enabled
L1 Entry is Enabled
L0s and L1 Entry Enabled
Possible Values
000001b, 000010b, 000100b
000001b
000001b
000001b
000001b, 000010b
000001b
Description
Description
Attribute:
Size:
RO
16 bits
®
ICH7 uses
683