876784 Intel, 876784 Datasheet - Page 420

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

10.8.1.2
420
GEN_PMCON_2—General PM Configuration 2 Register
(PM—D31:F0)
Offset Address: A2h
Default Value:
Lockable:
(Mobile/
(Mobile/
Mobile
Mobile
6:5
Bit
Only)
Only)
Ultra
Ultra
7
1:0
Bit
3
2
DRAM Initialization Bit — R/W. This bit does not effect hardware functionality in any
way. BIOS is expected to set this bit prior to starting the DRAM initialization sequence
and to clear this bit after completing the DRAM initialization sequence. BIOS can detect
that a DRAM initialization sequence was interrupted by a reset by reading this bit during
the boot sequence.
CPU PLL Lock Time (CPLT) — R/W. This field indicates the amount of time that the
processor needs to lock its PLLs. This is used wherever timing t270
applies.
00 = min 30.7 µs (Default)
01 = min 61.4 µs
10 = min 122.8 µs
11 = min 245.6 µs
It is the responsibility of the BIOS to program the correct value in this field prior to the
first transition to C3 or C4 states (or performing Intel SpeedStep
transitions).
NOTE: The new DPSLP-TO-SLP bits (D31:FO:AAh, bits 1:0) act as an override to these
NOTE: These bits are not cleared by any type of reset except RSMRST# or a CF9 write
• If the bit is 1, then the DRAM initialization was interrupted.
• This bit is reset by the assertion of the RSMRST# pin.
Intel SpeedStep Enable (SS_EN) — R/W.
0 = Intel SpeedStep technology logic is disabled and the SS_CNT register will not be
1 = Intel SpeedStep technology logic is enabled.
PCI CLKRUN# Enable (CLKRUN_EN) — R/W.
0 = Disable. Intel
1 = Enable CLKRUN# logic to control the system PCI clock via the CLKRUN# and
NOTE: when the SLP_EN# bit is set, the ICH7 drives the CLKRUN# signal low
Periodic SMI# Rate Select (PER_SMI_SEL) — R/W. Set by software to control
the rate at which periodic SMI# is generated.
00 = 1 minute
01 = 32 seconds
10 = 16 seconds
11 = 8 seconds
visible (reads to SS_CNT will return 00h and writes will have no effect).
STP_PCI# signals.
bits.
00h
No
regardless of the state of the CLKRUN_EN bit. This ensures that the PCI and
LPC clocks continue running during a transition to a sleep state.
®
ICH7-M/ICH7-U drives the CLKRUN# signal low.
Description
Description
Attribute:
Size:
Usage:
Power Well:
LPC Interface Bridge Registers (D31:F0)
Intel
R/W, R/WC
8-bit
ACPI, Legacy
Resume
®
®
ICH7 Family Datasheet
technology
(Chapter
23)