876784 Intel, 876784 Datasheet - Page 76

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

Table 2-22. Power and Ground Signals (Sheet 3 of 3)
2.24
2.24.1
Table 2-23. Functional Strap Definitions (Sheet 1 of 3)
76
Pin Straps
Functional Straps
The following signals are used for static configuration. They are sampled at the rising
edge of PWROK to select configurations (except as noted), and then revert later to their
normal usage. To invoke the associated mode, the signal should be driven at least four
PCI clocks prior to the time it is sampled.
(Desktop and
(Desktop and
ACZ_SDOUT
Mobile Only)
Mobile Only)
VccSATAPLL
ACZ_SYNC
and Mobile
VccUSBPLL
VccDMIPLL
V_CPU_IO
(Desktop
Signal
VccRTC
EE_CS
Name
Only)
Vss
PCI Express
Port Config
Port Config
XOR Chain
Entrance /
This pin provides the 3.3 V (can drop to 2.0 V min. in G3 state) supply for the
RTC well (1 pin). This power is not expected to be shut off unless the RTC
battery is removed or completely drained.
NOTE: Implementations should not attempt to clear CMOS by using a jumper to
This pin provides the 1.5 V supply for core well logic (1 pin). This signal is used
for the USB PLL. This power may be shut off in S3, S4, S5 or G3 states. Must be
powered even if USB not used.
This pin provides the 1.5 V supply for core well logic (1 pin). This signal is used
for the DMI PLL. This power may be shut off in S3, S4, S5 or G3 states.
This pin provides the 1.5 V supply for core well logic (1 pin). This signal is used
for the SATA PLL. This power may be shut off in S3, S4, S5 or G3 states. Must
be powered even if SATA not used.
These pins are powered by the same supply as the processor I/O voltage (3
pins). This supply is used to drive the processor interface signals listed in
Table
Grounds (194 pins).
Reserved
Express*
Usage
bit 1
bit 0
PCI
2-13.
pull VccRTC low. Clearing CMOS in an Intel
done by using a jumper on RTCRST# or GPI.
Rising Edge of
Rising Edge of
Sampled
PWROK
PWROK
When
Allows entrance to XOR Chain testing when TP3
pulled low at rising edge of PWROK. See
for XOR Chain functionality information.
When TP3 not pulled low at rising edge of PWROK,
sets bit 1 of RPC.PC (Chipset Configuration
Registers:Offset 224h). See
details.
This signal has a weak internal pull-down.
This signal has a weak internal pull-down.
Sets bit 0 of RPC.PC (Chipset Configuration
Registers:Offset 224h). See
details.
This signal has a weak internal pull-down.
NOTE: This signal should not be pulled high.
Description
®
Comment
Intel
ICH7-based platform can be
®
Section 7.1.34
Section 7.1.34
ICH7 Family Datasheet
Signal Description
Chapter 25
for
for