876784 Intel, 876784 Datasheet - Page 214

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

5.20.8.4
5.20.9
5.20.10
214
Effect of Resets on Port-Routing Logic
As mentioned above, the Port Routing logic is implemented in the suspend power well
so that remuneration and re-mapping of the USB ports is not required following
entering and exiting a system sleep state in which the core power is turned off.
USB 2.0 Legacy Keyboard Operation
The ICH7 must support the possibility of a keyboard downstream from either a full-
speed/low-speed or a high-speed port. The description of the legacy keyboard support
is unchanged from USB 1.1 (See
The EHC provides the basic ability to generate SMIs on an interrupt event, along with
more sophisticated control of the generation of SMIs.
USB 2.0 Based Debug Port
The ICH7 supports the elimination of the legacy COM ports by providing the ability for
new debugger software to interact with devices on a USB 2.0 port.
High-level restrictions and features are:
The Debug port facilitates operating system and device driver debug. It allows the
software to communicate with an external console using a USB 2.0 connection.
Because the interface to this link does not go through the normal USB 2.0 stack, it
allows communication with the external console during cases where the operating
system is not loaded, the USB 2.0 software is broken, or where the USB 2.0 software is
being debugged. Specific features of this implementation of a debug port are:
Suspend Well Reset
Core Well Reset
D3-to-D0 Reset
HCRESET
• Operational before USB 2.0 drivers are loaded.
• Functions even when the port is disabled.
• Works even though non-configured port is default-routed to the UHCI. Note that
• Allows normal system USB 2.0 traffic in a system that may only have one USB port.
• Debug Port device (DPD) must be high-speed capable and connect directly to Port
• Debug Port FIFO always makes forward progress (a bad status on USB is simply
• The Debug Port FIFO is only given one USB access per microframe.
• Only works with an external USB 2.0 debug device (console)
• Implemented for a specific port on the host controller
• Operational anytime the port is not suspended AND the host controller is in D0
• Capability is interrupted when port is driving USB RESET
the Debug Port can not be used to debug an issue that requires a full-speed/low-
speed device on Port #0 using the UHCI drivers.
#0 on ICH7 systems (e.g., the DPD cannot be connected to Port #0 thru a hub).
presented back to software).
power state.
Reset Event
cleared (0)
no effect
no effect
cleared (0)
Effect on Configure Flag
Section
5.19.8).
set (1)
no effect
no effect
set (1)
Effect on Port Owner Bits
Intel
®
ICH7 Family Datasheet
Functional Description