876784 Intel, 876784 Datasheet - Page 749

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

Intel® High Definition Audio Controller Registers (D27:F0)
19.2.34
19.2.35
Intel
®
ICH7 Family Datasheet
DPLBASE—DMA Position Lower Base Address Register
(Intel
Memory Address:HDBAR + 70h
Default Value:
DPUBASE—DMA Position Upper Base Address Register
(Intel
Memory Address:HDBAR + 74h
Default Value:
31:7
31:0
6:1
Bit
Bit
0
DMA Position Lower Base Address — R/W. Lower 32 bits of the DMA Position Buffer
Base Address. This register field must not be written when any DMA engine is running
or the DMA transfer may be corrupted. This same address is used by the Flush Control
and must be programmed with a valid value before the Flush Control bit
(HDBAR+08h:bit 1) is set.
DMA Position Lower Base Unimplemented bits — RO. Hardwired to 0 to force the 128-
byte buffer alignment for cache line write optimizations.
DMA Position Buffer Enable — R/W.
0 = Disable.
1 = Enable. The controller will write the DMA positions of each of the DMA engines to
DMA Position Upper Base Address — R/W. Upper 32 bits of the DMA Position Buffer
Base Address. This register field must not be written when any DMA engine is running
or the DMA transfer may be corrupted.
®
®
High Definition Audio Controller—D27:F0)
High Definition Audio Controller—D27:F0)
the buffer in the main memory periodically (typically once per frame). Software can
use this value to dtermine what data in memory is valid data.
00000000h
00000000h
Description
Description
Attribute:
Size:
Attribute:
Size:
R/W, RO
32 bits
R/W
32 bits
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