876784 Intel, 876784 Datasheet - Page 574

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

574
This register is in the suspend power well. It is only reset by hardware when the
suspend power is initially applied or in response to a host controller reset. The initial
conditions of a port are:
When a device is attached, the port state transitions to the attached state and system
software will process this as with any status change notification. Refer to Section 4 of
the EHCI specification for operational requirements for how change events interact with
port suspend mode.
31:23
19:16
15:14
• No device connected
• Port disabled.
Bit
22
21
20
13
Reserved. These bits are reserved for future use and will return a value of 0’s when
read.
Wake on Overcurrent Enable (WKOC_E) — R/W.
0 = Disable. (Default)
1 = Enable. Writing this bit to a 1 enables the setting of the PME Status bit in the Power
Wake on Disconnect Enable (WKDSCNNT_E) — R/W.
0 = Disable. (Default)
1 = Enable. Writing this bit to a 1 enables the setting of the PME Status bit in the Power
Wake on Connect Enable (WKCNNT_E) — R/W.
0 = Disable. (Default)
1 = Enable. Writing this bit to a 1 enables the setting of the PME Status bit in the Power
Port Test Control — R/W. When this field is 0’s, the port is NOT operating in a test
mode. A non-zero value indicates that it is operating in test mode and the specific test
mode is indicated by the specific value. The encoding of the test mode bits are (0110b
– 1111b are reserved):
Refer to USB Specification Revision 2.0, Chapter 7 for details on each test mode.
Reserved — R/W. Should be written to =00b.
Port Owner — R/W. Default = 1b. This bit unconditionally goes to a 0 when the
Configured Flag bit in the USB2.0_CMD register makes a 0 to 1 transition.
System software uses this field to release ownership of the port to a selected host
controller (in the event that the attached device is not a high-speed device). Software
writes a 1 to this bit when the attached device is not a high-speed device. A 1 in this bit
means that a companion host controller owns and controls the port. See Section 4 of
the EHCI Specification for operational details.
Value
0000b
0001b
0010b
0011b
0100b
0101b
Management Control/Status Register (offset 54, bit 15) when the overcurrent
Active bit (bit 4 of this register) is set.
Management Control/Status Register (offset 54, bit 15) when the Current Connect
Status changes from connected to disconnected (i.e., bit 0 of this register changes
from 1 to 0).
Management Control/Status Register (offset 54, bit 15) when the Current Connect
Status changes from disconnected to connected (i.e., bit 0 of this register changes
from 0 to 1).
Test mode not enabled (default)
Maximum Interrupt Interval
FORCE_ENABLE
Test SE0_NAK
Test K_STATE
Test J_STATE
Test Packet
Description
EHCI Controller Registers (D29:F7)
Intel
®
ICH7 Family Datasheet