876784 Intel, 876784 Datasheet - Page 491

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876784

Manufacturer Part Number
876784
Description
Manufacturer
Intel
Datasheet

Specifications of 876784

Lead Free Status / RoHS Status
Compliant
SATA Controller Registers (D31:F2) (Desktop and Mobile Only)
12.1.1
12.1.2
12.1.3
Intel
®
ICH7 Family Datasheet
VID—Vendor Identification Register (SATA—D31:F2)
Offset Address: 00h
Default Value:
Lockable:
DID—Device Identification Register (SATA—D31:F2)
Offset Address: 02h
Default Value:
Lockable:
PCICMD—PCI Command Register (SATA–D31:F2)
Address Offset: 04h
Default Value:
15:11
15:0
15:0
Bit
10
Bit
Bit
9
8
7
6
5
4
3
Reserved
Interrupt Disable — R/W. This disables pin-based INTx# interrupts. This bit has no
effect on MSI operation.
0 = Internal INTx# messages are generated if there is an interrupt and MSI is not
1 = Internal INTx# messages will not be generated.
Fast Back to Back Enable (FBE) — RO. Reserved as 0.
SERR# Enable (SERR_EN) — RO. Reserved as 0.
Wait Cycle Control (WCC) — RO. Reserved as 0.
Parity Error Response (PER) — R/W.
0 = Disabled. SATA controller will not generate PERR# when a data parity error is
1 = Enabled. SATA controller will generate PERR# when a data parity error is detected.
VGA Palette Snoop (VPS) — RO. Reserved as 0.
Postable Memory Write Enable (PMWE) — RO. Reserved as 0.
Special Cycle Enable (SCE) — RO. Reserved as 0.
Vendor ID — RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h
Device ID — RO. This is a 16-bit value assigned to the Intel
NOTE: The value of this field will change dependent upon the value of the MAP
enabled.
detected.
Register. Refer to the Intel
Update and
8086h
No
See bit description
No
0000h
01h
03h
05h
Section 12.1.33
®
I/O Controller Hub 7 (ICH7) Family Specification
Description
Description
Description
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
Attribute:
Size:
®
RO
16 bit
Core
RO
16 bit
Core
RO, R/W
16 bits
ICH7 SATA controller.
491

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