876784 Intel, 876784 Datasheet - Page 587

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

SMBus Controller Registers (D31:F3)
14.1.10
14.1.11
14.1.12
14.1.13
Intel
®
ICH7 Family Datasheet
SVID — Subsystem Vendor Identification Register
(SMBUS—D31:F2/F4)
Address Offset: 2Ch
Default Value:
Lockable:
SID — Subsystem Identification Register
(SMBUS—D31:F2/F4)
Address Offset: 2Eh
Default Value:
Lockable:
INT_LN—Interrupt Line Register (SMBUS—D31:F3)
Address Offset: 3Ch
Default Value:
INT_PN—Interrupt Pin Register (SMBUS—D31:F3)
Address Offset: 3Dh
Default Value:
15:0
15:0
7:0
Bit
Bit
Bit
7:0
Bit
Subsystem Vendor ID (SVID) — RO. The SVID register, in combination with the
Subsystem ID (SID) register, enables the operating system (OS) to distinguish
subsystems from each other. The value returned by reads to this register is the same as
that which was written by BIOS into the IDE SVID register.
NOTE: Software can write to this register only once per core well reset. Writes should
Subsystem ID (SID) — RO. The SID register, in combination with the SVID register,
enables the operating system (OS) to distinguish subsystems from each other. The
value returned by reads to this register is the same as that which was written by BIOS
into the IDE SID register.
NOTE: Software can write to this register only once per core well reset. Writes should
Interrupt Line (INT_LN) — R/W. This data is not used by the Intel
communicate to software the interrupt line that the interrupt pin is connected to
PIRQB#.
Interrupt PIN (INT_PN) — RO. This reflects the value of D31IP.SMIP in chipset
configuration space.
be done as a single 16-bit cycle.
be done as a single 16-bit cycle.
0000h
No
00h
No
00h
See description
–
–
2Fh
2Dh
Description
Description
Description
Description
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
Attributes:
Size:
Attributes:
Size:
RO
16 bits
Core
R/WO
16 bits
Core
R/W
8 bits
RO
8 bits
®
ICH7. It is to
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