876784 Intel, 876784 Datasheet - Page 676

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

18.1.21
676
BCTRL—Bridge Control Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 3Eh–3Fh
Default Value:
15:12
Bit
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
Discard Timer SERR# Enable (DTSE). Reserved per PCI Express* Base Specification,
Revision 1.0a
Discard Timer Status (DTS). Reserved per PCI Express* Base Specification, Revision
1.0a.
Secondary Discard Timer (SDT). Reserved per PCI Express* Base Specification,
Revision 1.0a.
Primary Discard Timer (PDT). Reserved per PCI Express* Base Specification, Revision
1.0a.
Fast Back to Back Enable (FBE). Reserved per PCI Express* Base Specification, Revision
1.0a.
Secondary Bus Reset (SBR) — R/W. This bit triggers a hot reset on the PCI Express*
port.
Master Abort Mode (MAM): Reserved per Express specification.
VGA 16-Bit Decode (V16) — R/W.
0 = VGA range is enabled.
1 = The I/O aliases of the VGA range (see BCTRL:VE definition below), are not enabled,
VGA Enable (VE)— R/W.
0 = The ranges below will not be claimed off the backbone by the root port.
1 = The following ranges will be claimed off the backbone by the root port:
ISA Enable (IE) — R/W. This bit only applies to I/O addresses that are enabled by the
I/O Base and I/O Limit registers and are in the first 64 KB of PCI I/O space.
0 = The root port will not block any forwarding from the backbone as described below.
1 = The root port will block any forwarding from the backbone to the device of I/O
SERR# Enable (SE) — R/W.
0 = The messages described below are not forwarded to the backbone.
1 = ERR_COR, ERR_NONFATAL, and ERR_FATAL messages received are forwarded to
Parity Error Response Enable (PERE) — R/W.
0 = Poisoned write TLPs and completions indicating poisoned TLPs will not set the
1 = Poisoned write TLPs and completions indicating poisoned TLPs will set the
— Memory ranges A0000h–BFFFFh
— I/O ranges 3B0h – 3BBh and 3C0h – 3DFh, and all aliases of bits 15:10 in any combination
and only the base I/O ranges can be decoded
transactions addressing the last 768 bytes in each 1-KB block (offsets 100h to
3FFh).
the backbone.
SSTS.DPD (D28:F0/F1/F2/F3/F4/F5:1E, bit 8).
SSTS.DPD (D28:F0/F1/F2/F3/F4/F5:1E, bit 8).
of 1s
0000h
PCI Express* Configuration Registers (Desktop and Mobile Only)
Description
Attribute:
Size:
Intel
R/W
16 bits
®
ICH7 Family Datasheet