876784 Intel, 876784 Datasheet - Page 500

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

500
13:12
11:10
9:8
Bit
15
14
7
6
5
4
3
2
IDE Decode Enable (IDE) — R/W. Individually enable/disable the Primary or
Secondary decode.
0 = Disable.
1 = Enables the Intel
This bit effects the IDE decode ranges for both legacy and native-Mode decoding.
NOTE: This bit affects SATA operation in both combined and non-combined ATA modes.
Drive 1 Timing Register Enable (SITRE) — R/W.
0 = Use bits 13:12, 9:8 for both drive 0 and drive 1.
1 = Use bits 13:12, 9:8 for drive 0, and use the Slave IDE Timing register for drive 1
IORDY Sample Point (ISP) — R/W. The setting of these bits determines the number
of PCI clocks between IDE IOR#/IOW# assertion and the first IORDY sample point.
00 = 5 clocks
01 = 4 clocks
10 = 3 clocks
11 = Reserved
Reserved
Recovery Time (RCT) — R/W. The setting of these bits determines the minimum
number of PCI clocks between the last IORDY sample point and the IOR#/IOW# strobe
of the next cycle.
00 = 4 clocks
01 = 3 clocks
10 = 2 clocks
11 = 1 clock
Drive 1 DMA Timing Enable (DTE1) — R/W.
0 = Disable.
1 = Enable the fast timing mode for DMA transfers only for this drive. PIO transfers to
Drive 1 Prefetch/Posting Enable (PPE1) — R/W.
0 = Disable.
1 = Enable Prefetch and posting to the IDE data port for this drive.
Drive 1 IORDY Sample Point Enable (IE1) — R/W.
0 = Disable IORDY sampling for this drive.
1 = Enable IORDY sampling for this drive.
Drive 1 Fast Timing Bank (TIME1) — R/W.
0 = Accesses to the data port will use compatible timings for this drive.
1 = When this bit =1 and bit 14 = 0, accesses to the data port will use bits 13:12 for
Drive 0 DMA Timing Enable (DTE0) — R/W.
0 = Disable
1 = Enable fast timing mode for DMA transfers only for this drive. PIO transfers to the
Drive 0 Prefetch/Posting Enable (PPE0) — R/W.
0 = Disable prefetch and posting to the IDE data port for this drive.
1 = Enable prefetch and posting to the IDE data port for this drive.
primary, 170–177h for secondary) and Control Block (3F6h for primary and 376h
for secondary).
the IDE data port will run in compatible timing.
the IORDY sample point, and bits 9:8 for the recovery time. When this bit = 1 and
bit 14 = 1, accesses to the data port will use the IORDY sample point and recover
time specified in the slave IDE timing register.
IDE data port will run in compatible timing.
See
Section 5.17
®
ICH7 to decode the associated Command Blocks (1F0–1F7h for
for more on ATA modes of operation.
SATA Controller Registers (D31:F2) (Desktop and Mobile Only)
Description
Intel
®
ICH7 Family Datasheet