876784 Intel, 876784 Datasheet - Page 236

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

Figure 5-14. AC-Link Protocol
5.22.2.1
236
Synchronization of all AC-link data transactions is signaled by the AC ’97 controller via
the ACZ_SYNC signal, as shown in
clock onto the AC-link, which the AC ’97 controller then qualifies with the ACZ_SYNC
signal to construct data frames. ACZ_SYNC, fixed at 48 kHz, is derived by dividing
down ACZ_BIT_CLK. ACZ_SYNC remains high for a total duration of 16 ACZ_BIT_CLK
at the beginning of each frame. The portion of the frame where ACZ_SYNC is high is
defined as the tag phase. The remainder of the frame where ACZ_SYNC is low is
defined as the data phase. Each data bit is sampled on the falling edge of
ACZ_BIT_CLK.
The ICH7 has three ACZ_SDIN pins allowing a single, dual, or triple codec
configuration. When multiple codecs are connected, the primary, secondary, and
tertiary codecs can be connected to any ACZ_SDIN line. The ICH7 does not distinguish
between codecs on its ACZ_SDIN[2:0] pins, however the registers do distinguish
between ACZ_SDIN[0], ACZ_SDIN[1], and ACZ_SDIN[2] for wake events, etc. If using
a Modem Codec it is recommended to connect it to ACZ_SDIN1.
The ICH7 does not support optional test modes as outlined in the AC ’97 Specification,
Version 2.3.
Register Access
In the ICH7 implementation of the AC-link, up to three codecs can be connected to the
SDOUT pin. The following mechanism is used to address the primary, secondary, and
tertiary codecs individually.
The primary device uses bit 19 of slot 1 as the direction bit to specify read or write. Bits
[18:12] of slot 1 are used for the register index. For I/O writes to the primary codec,
the valid bits [14:13] for slots 1 and 2 must be set in slot 0, as shown in
Slot 1 is used to transmit the register address, and slot 2 is used to transmit data. For
I/O reads to the primary codec, only slot 1 should be valid since only an address is
transmitted. For I/O reads only slot 1 valid bit is set, while for I/O writes both slots 1
and 2 valid bits are set.
The secondary and tertiary codec registers are accessed using slots 1 and 2 as
described above, however the slot valid bits for slots 1 and 2 are marked invalid in slot
0 and the codec ID bits [1:0] (bit 0 and bit 1 of slot 0) is set to a non-zero value. This
allows the secondary or tertiary codec to monitor the slot valid bits of slots 1 and 2, and
bits [1:0] of slot 0 to determine if the access is directed to the secondary or tertiary
codec. If the register access is targeted to the secondary or tertiary codec, slot 1 and 2
will contain the address and data for the register access. Since slots 1 and 2 are
marked invalid, the primary codec will ignore these accesses.
BIT_CLK
SDIN
SYNC
End of previous
Audio Frame
Codec
Ready
12.288 MHz
slot(1)
("1" = time slot contains valid PCM
Tag Phase
slot(2)
81.4 nS
Time Slot "Valid"
slot(12)
Bits
"0"
Figure
"0"
"0"
5-14. The primary codec drives the serial bit
19
Slot 1
0
(48 KHz)
20.8uS
19
Slot 2
Data Phase
0
Intel
19
Slot 3
®
ICH7 Family Datasheet
Functional Description
0
Table
19
Slot 12
5-60.
0