876784 Intel, 876784 Datasheet - Page 107

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

Functional Description
5.2.4.3
5.2.4.4
Intel
®
ICH7 Family Datasheet
Attention Button Detection
When an attached device is ejected, an attention button could be pressed by the user.
This attention button press will result in a the PCI Express message
“Attention_Button_Pressed” from the device. Upon receiving this message, the root
port will set SLSTS.ABP (D28:F0/F1/F2/F3F4/F5:Offset 5Ah:bit 0).
If SLCTL.ABE (D28:F0/F1/F2/F3F4/F5:Offset 58h:bit 0) and SLCTL.HPE (D28:F0/F1/F2/
F3F4/F5:Offset 58h:bit 5) are set, the Hot-Plug controller will also generate an
interrupt. The interrupt is generated on an edge-event. For example, if SLSTS.ABP is
already set, a new interrupt will not be generated.
SMI/SCI Generation
Interrupts for Hot-Plug events are not supported on legacy operating systems. To
support Hot-Plug on non-PCI Express aware operating systems, Hot-Plug events can be
routed to generate SCI. To generate SCI, MPC.HPCE (D28:F0/F1/F2/F3F4/F5:Offset
D8h:bit 30) must be set. When set, enabled Hot-Plug events will cause SMSCS.HPCS
(D28:F0/F1/F2/F3F4/F5:Offset DCh:bit 30) to be set.
Additionally, BIOS workarounds for Hot-Plug can be supported by setting MPC.HPME
(D28:F0/F1/F2/F3F4/F5:Offset D8h:bit 1). When this bit is set, Hot-Plug events can
cause SMI status bits in SMSCS to be set. Supported Hot-Plug events and their
corresponding SMSCS bit are:
When any of these bits are set, SMI # will be generated. These bits are set regardless
of whether interrupts or SCI is enabled for Hot-Plug events. The SMI# may occur
concurrently with an interrupt or SCI.
• Command Completed - SCSCS.HPCCM (D28:F0/F1/F2/F3/F4/F5:Offset DCh:bit 3)
• Presence Detect Changed - SMSCS.HPPDM (D28:F0/F1/F2/F3/F4/F5:Offset DCh:bit
• Attention Button Pressed - SMSCS.HPABM (D28:F0/F1/F2/F3/F4/F5:Offset DCh:bit
• Link Active State Changed - SMSCS.HPLAS (D28:F0/F1/F2/F3/F4/F5:Offset DCh:bit
1)
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