876784 Intel, 876784 Datasheet - Page 226

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

Table 5-53. Enables for the Host Notify Command
5.21.5
Note:
5.21.6
5.21.7
226
SMBALERT#
SMBALERT# is multiplexed with GPIO11. When enable and the signal is asserted, The
ICH7 can generate an interrupt, an SMI#, or a wake event from S1
Any event on SMBALERT# (regardless whether it is programmed as a GPI or not),
causes the event message to be sent in heartbeat mode.
SMBus CRC Generation and Checking
If the AAC bit is set in the Auxiliary Control register, the ICH7 automatically calculates
and drives CRC at the end of the transmitted packet for write cycles, and will check the
CRC for read cycles. It will not transmit the contents of the PEC register for CRC. The
PEC bit must not be set in the Host Control register if this bit is set, or unspecified
behavior will result.
If the read cycle results in a CRC error, the DEV_ERR bit and the CRCE bit in the
Auxiliary Status register at offset 0Ch will be set.
SMBus Slave Interface
The ICH7’s SMBus Slave interface is accessed via the SMBus. The SMBus slave logic will
not generate or handle receiving the PEC byte and will only act as a Legacy Alerting
Protocol device. The slave interface allows the ICH7 to decode cycles, and allows an
external microcontroller to perform specific actions. Key features and capabilities
include:
HOST_NOTIFY_INTRE
• Supports decode of three types of messages: Byte Write, Byte Read, and Host
• Receive Slave Address register: This is the address that the ICH7 decodes. A
• Receive Slave Data register in the SMBus I/O space that includes the data written
• Registers that the external microcontroller can read to get the state of the ICH7.
• Status bits to indicate that the SMBus slave logic caused an interrupt or SMI# due
N (Slave Control I/O
Register, Offset 11h,
Notify.
default value is provided so that the slave interface can be used without the
processor having to program this register.
by the external microcontroller.
to the reception of a message that matched the slave address.
— Bit 0 of the Slave Status Register for the Host Notify command
— Bit 16 of the SMI Status Register
bit 0)
X
0
1
1
D31:F3:Off40h, Bit
SMB_SMI_EN
(Host Config
Register,
1)
X
X
0
1
(Section
HOST_NOTIFY_WKEN
Register, Offset 11h,
(Slave Control I/O
10.8.3.13) for all others
bit 1)
0
1
X
X
Intel
®
ICH7 Family Datasheet
–
Functional Description
S5.
None
Wake generated
Interrupt generated
Slave SMI#
generated
(SMBUS_SMI_STS)
Result