876784 Intel, 876784 Datasheet - Page 158

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

Table 5-28. Causes of SMI# and SCI (Sheet 2 of 2)
158
NOTES:
1.
2.
3.
4.
5.
6.
7.
TCO SMI — NMI occurred
(and NMIs mapped to SMI)
TCO SMI — INTRUDER#
signal goes active
TCO SMI — Change of the
BIOSWP bit from 0 to 1
TCO SMI — Write attempted
to BIOS
BIOS_RLS written to
GBL_RLS written to
Write to B2h register
Periodic timer expires
64 ms timer expires
Enhanced USB Legacy
Support Event
Enhanced USB Intel Specific
Event
UHCI USB Legacy logic
Serial IRQ SMI reported
Device monitors match
address in its range
SMBus Host Controller
SMBus Slave SMI message
SMBus SMBALERT# signal
active
SMBus Host Notify message
received
(Mobile/Ultra Mobile Only)
BATLOW# assertion
Access microcontroller 62h/
66h
SLP_EN bit written to 1
SCI_EN must be 1 to enable SCI. SCI_EN must be 0 to enable SMI.
GBL_SMI_EN must be 1 to enable SMI.
IICH7 must have SMI# fully enabled when ICH7 is also enabled to trap cycles. If SMI# is
When a power button override first occurs, the system will transition immediately to S5.
The SCI will only occur after the next wake to S0 if the residual status bit (PRBTNOR_STS)
is not cleared prior to setting SCI_EN.
Only GPI[15:0] may generate an SMI# or SCI.
SCI can be routed to cause interrupt 9:11 or 20:23 (20:23 only available in APIC mode).
EOS must be written to 1 to re-enable SMI for the next 1.
not enabled in conjunction with the trap enabling, then hardware behavior is undefined.
Cause
1-5
No
No
No
No
Yes
No
No
No
No
No
No
No
No
No
No
No
No
No
Yes
No
No
SCI
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
SMI
NMI2SMI_EN=1
INTRD_SEL=10
BLD=1
BIOSWP=1
GBL_EN=1
BIOS_EN=1
APMC_EN = 1
PERIODIC_EN=1
SWSMI_TMR_EN=1
LEGACY_USB2_EN = 1
INTEL_USB2_EN = 1
LEGACY_USB_EN=1
none
none
SMB_SMI_EN
Host Controller Enabled
none
none
HOST_NOTIFY_INTREN
BATLOW_EN=1.
MCSMI_EN
SMI_ON_SLP_EN=1
Additional Enables
Intel
®
NMI2SMI_STS
INTRD_DET
BIOSWR_STS
BIOSWR_STS
GBL_STS
BIOS_STS
APM_STS
PERIODIC_STS
SWSMI_TMR_STS
LEGACY_USB2_STS
INTEL_USB2_STS
LEGACY_USB_STS
SERIRQ_SMI_STS
DEVMON_STS,
DEVACT_STS
SMBus host status
reg.
SMBUS_SMI_STS
SMBUS_SMI_STS
SMBUS_SMI_STS
HOST_NOTIFY_STS
BATLOW_STS
MCSMI_STS
SMI_ON_SLP_EN_STS
ICH7 Family Datasheet
Functional Description
Where Reported