EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 93

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Altera Corporation-Preliminary
March 2007
Figure 5–2. Multiplier Block Architecture
Input Registers
You can send each multiplier input signal into an input register or directly
into the multiplier in 9- or 18-bit sections, depending on the operational
mode of the multiplier. You can send each multiplier input signal through
a register independently of each other (for example, you can send the
multiplier’s data A signal through a register and send the data B signal
directly to the multiplier). The following control signals are available to
each input register within the embedded multiplier:
■
■
■
All input and output registers within a single embedded multiplier are
fed by the same clock, clock enable, and asynchronous clear signals.
Multiplier Stage
The multiplier stage of an embedded multiplier block supports 9 x 9 or
18 x 18 multipliers as well as other multipliers in between these
configurations. Depending on the data width or operational mode of the
multiplier, a single embedded multiplier can perform one or two
multiplications in parallel.
Data A
Data B
clock
clock enable
asynchronous clear
ENA
ENA
D
D
CLRN
CLRN
signa
signb
clock
Q
Q
ena
aclr
Register
Input
Embedded Multiplier Block
Cyclone III Device Handbook, Volume 1
ENA
D
CLRN
Register
Output
Q
Architecture
Data Out
5–5