EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 57

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Altera Corporation-Preliminary
March 2007
Table 4–2
in each Cyclone III device family member.
Control Signals
Figure 4–1
implemented in the Cyclone III memory block.
The clock-enable control signal controls clock entering for the entire
memory block, not just the input and output registers. This signal
disables the clock so that the memory block does not see any clock edges
and will not perform any operations.
The read-enable (rden) and write-enable (wren) control signals control
the read and write operations for each port of the memory blocks. You can
disable read-enable or write-enable signals independently to save power
whenever the operation is not required.
EP3C5
EP3C10
EP3C16
EP3C25
EP3C40
EP3C55
EP3C80
EP3C120
Table 4–2. Number of M9K Blocks in Cyclone III Devices
Device
shows the capacity and distribution of the M9K memory blocks
shows how the register clocks, clears, and control signals are
Number of M9K Blocks
126
260
305
432
46
46
56
66
Cyclone III Device Handbook, Volume 1
Total RAM Bits
1,161,216
2,396,160
2,810,880
3.981,312
423,936
423,936
516,096
608,256
Overview
4–3