EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 382

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

IEEE 1149.1 (JTAG) Boundary-Scan Testing for Cyclone III Devices
14–8
Cyclone III Device Handbook, Volume 1
BYPASS
USERCODE
IDCODE
HIGHZ
CLAMP
ICR instructions
PULSE_NCONFIG
CONFIG_IO
ACTIVE_DISENGAGE
ACTIVE_ENGAGE
APFC_BOOT_ADDR
Table 14–4. Cyclone III JTAG Instructions
JTAG Instruction
(2)
(2)
(2)
(2)
Instruction Code
11 1111 1111
00 0000 0111
00 0000 0110
00 0000 1011
00 0000 1010
00 0000 0001
00 0000 1101
10 1101 0000
10 1011 0000
10 0111 0000
Places the 1-bit bypass register between the
pins, which allows the BST data to pass synchronously through
selected devices to adjacent devices during normal device
operation.
Selects the 32-bit
TDI
shifted out of
Selects the
TDO
Places the 1-bit bypass register between the
which allows the
selected devices to adjacent devices during normal device
operation, while tri-stating all of the I/O pins.
Places the 1-bit bypass register between the
which allows the
selected devices to adjacent devices during normal device
operation while holding I/O pins to a state defined by the data in
the boundary-scan register.
Used when configuring a Cyclone III device via the JTAG port
with a USB Blaster
ByteBlasterMV
JBC File via an embedded processor.
Emulates pulsing the
reconfiguration even though the physical pin is unaffected.
Allows I/O reconfiguration through JTAG ports using the
for JTAG testing. Can be executed after or during
configurations.
the
prior to CONFIG_IO to configure the IOCSR or perform board
level testing.
This instruction may need to be used in AS and AP
configuration schemes to re-engage the active controller.
Places the 22-bit active boot address register between the
and
shifted into
controller. In remote system upgrade, the
instruction sets the boot address for the factory configuration.
Places the active configuration mode controllers into idle state
CONFIG_IO
, allowing the
TDO
and
pins, allowing a new active boot address to be serially
TDO
TDI
IDCODE
TDO
pins, allowing the
TM
nSTATUS
BST
BST
instruction.
and into the active parallel (AP) flash
USERCODE
download cable, or when using a Jam File, or
.
IDCODE
TM
nCONFIG
ByteBlaster
register and places it between
data to pass synchronously through
data to pass synchronously through
Description
pin must go high before you can issue
to be serially shifted out of
register and places it between the
Altera Corporation-Preliminary
USERCODE
pin low to trigger
TM
II, MasterBlaster
APFC_BOOT_ADDR
TDI
TDI
to be serially
TDI
and
and
March 2007
and
TDI
TM
TDO
TDO
TDO
IOCSR
or
TDO
and
pins,
pins,
TDI
.