EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 121

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Clock Feedback
Modes
Altera Corporation-Preliminary
March 2007
Cyclone III PLLs support up to four different clock feedback modes. Each
mode allows clock multiplication and division, phase shifting, and
programmable duty cycle.
1
Source-Synchronous Mode
If data and clock arrive at the same time at the input pins, the phase
relationship between them remains the same at the clock and data ports
of any I/O element input register.
waveform of the clock and data in this mode. You should use this mode
for source-synchronous data transfers. Data and clock signals at the I/O
element experience similar buffer delays as long as the same I/O
standard is used.
Figure 6–11. Phase Relationship Between Clock and Data
in Source-Synchronous Mode
The input/output delays are fully compensated by the PLL only
when using the dedicated clock input pins associated with a
given PLL as the clock sources. For example, when using PLL1
in normal mode, the clock delays from the input pin to PLL
and PLL clock output-to-destination register are fully
compensated provided the clock input pin is one of the
following four pins: CLK0, CLK1, CLK2, or CLK3. When driving
the PLL using the GCLK network, the input/output delays may
not be fully compensated in the Quartus II software.
PLL reference
clock at input pin
Data pin
Data at register
Clock at register
Figure 6–11
Cyclone III Device Handbook, Volume 1
shows an example
Clock Feedback Modes
6–21