EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 232

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

External Memory Interfaces in Cyclone III Devices
Figure 9–8. Extending the OE Disable by Half a Clock Cycle for a Write Transaction
Note to
(1)
9–18
Cyclone III Device Handbook, Volume 1
The waveform reflects the software simulation result. The OE signal is an active low on the device. However, the
Quartus II software implements the signal as an active high and automatically adds an inverter before the A
register D input.
Figure
9–8:
f
On-Chip Termination (OCT)
Cyclone III supports calibrated on-chip series termination (OCT R
both vertical and horizontal I/O banks. To use the calibrated OCT, you
need to use the R
each side). You can use each OCT calibration block to calibrate one type
of termination with the same V
For more information on the Cyclone III OCT calibration block, refer to
the Cyclone III Device I/O Features chapter in volume 1 of the Cyclone III
Device Handbook.
PLL
When interfacing with external memory, the PLL is used to generate the
memory system clock, the write clock, the capture clock and the
logic-core clock. The system clock generates the DQS write signals,
commands, and addresses. The write-clock is shifted by –90° from the
UP
and R
DN
pins for each OCT R
CCIO
for that given side.
Altera Corporation-Preliminary
S
Note (1)
control block (one for
March 2007
S
) in
OE