EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 101

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Introduction
Clock Networks
Altera Corporation-Preliminary
March 2007
CIII51007-1.0
Cyclone
combination with the clock synthesis precision provided by phase-locked
loops (PLLs). This provides a complete clock-management solution.
Cyclone III devices provide up to 20 dedicated global clock networks
(GCLK). Clock networks that are not being used in the design are
automatically turned off in the Quartus
power consumption. Cyclone III devices include up to four PLLs per
device and up to five outputs per PLL. The additional global clock
networks and additional PLL outputs compared to Cyclone II devices
enables more efficient use of PLL resources. You can independently
program every output, creating a unique, customizable clock frequency
with no fixed relation to any other input or output clock. Inherent jitter
filtration and fine granularity control over multiply, divide ratios, and
dynamic phase shift reconfiguration provide the high performance
precision required in today's high-speed applications.
Cyclone III device PLLs are feature rich, supporting advanced
capabilities such as clock switchover, dynamic phase shifting, and PLL
reconfiguration. Dynamic phase reconfiguration allows implementation
of high performance, easy to implement, and self calibrating external
memory interfaces. Dynamic phase reconfiguration allows support for
advanced display applications where the PLL input frequency may not be
known ahead of time or may change. Cyclone III PLLs also support
spread-spectrum tracking to support clock sources that lower EMI. The
Altera
any external devices. The following sections describe the Cyclone III
clock networks and PLLs in detail.
Cyclone III devices provide up to 16 dedicated clock pins (CLK[15..0])
that can drive the global clock networks. The smaller Cyclone III devices
(EP3C5 and EP3C10) support four dedicated clock pins on the left and
right sides of the device, capable of driving a total of ten global clock
networks. The larger devices (EP3C16 devices and larger) support four
dedicated clock pins on each side of the device. These clock pins can drive
20 global clock networks.
®
Quartus II software enables the PLL features without requiring
®
III devices provide a large number of global clock resources in
6. Clock Networks and PLLs
in Cyclone III Devices
®
II software to reduce overall
6–1