EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 283

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Figure 10–14. Single Device PS Configuration Using an External Host
Notes to
(1)
(2)
(3)
(4)
Altera Corporation-Preliminary
March 2007
Connect the pull-up resistor to a supply that provides an acceptable input signal for the device. V
enough to meet the V
The nCEO pin can be left unconnected or used as a user I/O pin when it does not feed other device’s nCE pin.
The MSEL pin settings vary for different configuration voltage standards and POR time. To connect MSEL[3..0],
refer to
All I/O inputs must maintain a maximum AC voltage of 4.1 V. The DATA[0] and DCLK has to fit the maximum
overshoot equation outlined in
Figure
Table 10–10 on page
10–14:
f
(MAX II Device or
Microprocessor)
External Host
IH
specification of the I/O on the device and the external host.
ADDR
can store configuration data RBF, HEX, or TTF format.
shows the configuration interface connections between a Cyclone III
device and a MAX II device for single device configuration.
1
Upon power-up, the Cyclone III devices go through a POR. The POR
delay is dependent on the MSEL pin settings which correspond to the
configuration scheme that you select. Depending on the configuration
scheme, either a fast POR time or a standard POR time is available. The
fast POR time is 3ms < T
standard POR time is 50ms < T
ramp rate. During POR, the device resets, holds nSTATUS low, and tri-
states all user I/O pins. Once the device successfully exits POR, all user
I/O pins continue to be tri-stated. The user I/O pins and dual-purpose
I/O pins have weak pull-up resistors which are always enabled (after
POR) before and during configuration.
For information about the value of the weak pull-up resistors on the I/O
pins that are on before and during configuration can be found in the DC
and Switching Characteristics chapter of the Cyclone III Device Handbook.
10–46. Connect the MSEL pins directly to V
Memory
“Configuration and JTAG Pin I/O Requirements” on page
DATA[0]
All I/O inputs must maintain a maximum AC voltage of 4.1 V.
In single device PS configuration, the DATA[0] and DCLK has to
fit the maximum overshoot equation outlined in
and JTAG Pin I/O Requirements” on page
10kΩ
V
CCIO (1)
10kΩ
V
GND
CCIO (1)
POR
< 9 ms for fast configuration time. The
CONF_DONE
nSTATUS
nCE
Cyclone III Device
DATA[0] (4)
nCONFIG
DCLK (4)
POR
< 200ms which has a lower power
Cyclone III Device Handbook, Volume 1
MSEL[3..0]
CCIO
nCEO
or ground.
Passive Serial Configuration
N.C. (2)
(3)
10–13.
10–13.
Figure 10–14
“Configuration
CC
should be high
10–47