EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 199

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Figure 8–6. Receiver Input Waveforms for the LVDS Differential I/O Standard
Note to
(1)
Altera Corporation-Preliminary
March 2007
The p – n waveform is a function of the positive channel (
Figure
Differential Waveform (Mathematical Function of Positive & Negative Channel)
Single-Ended Waveform
8–6:
f
V
ICM
Figure 8–6
RSDS I/O Standard Support in Cyclone III Devices
The RSDS specification is used in chip-to-chip applications between the
timing controller and the column drivers on the display panels.
Cyclone III devices meet the National Semiconductor Corporation RSDS
Interface Specification and support the RSDS output standard. All the
Cyclone III device I/O banks support the RSDS output standard. The left
and right I/O banks support dedicated RSDS transmitters which are able
to run at up to 360 Mbps. On the top and bottom I/O banks, the RSDS
transmitters are supported using external resistors. The performance
target is pending device characterization. The RSDS standard does not
require an input reference voltage; however, it does require a 100-Ω
termination resistor between the two signals at the input buffer.
See the Cyclone III Device Datasheet: DC and Switching Characteristics
chapter in volume 2 of the Cyclone III Device Handbook for the RSDS I/O
standard electrical specifications.
V ID
shows the signaling level for LVDS receiver inputs.
V ID
V
ID
p
) and the negative channel (
V ID
Cyclone III Device Handbook, Volume 1
0 V
p − n (1)
High-Speed I/O Standards Support
Positive Channel (p) = V
Negative Channel (n) = V
Ground
n
).
OH
OL
8–9