EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 437

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Cyclone III Device Datasheet: DC & Switching Characteristics
Altera Corporation-Preliminary
March 2007
Notes to
(1)
(2)
(3)
(4)
(5)
f
HSIODR
t
TCCS
Output jitter (peak to peak)
t
t
t
HSCLK
DUTY
RISE
FALL
LOCK
Table 1–33. Three-Resistor LVDS Transmitter Timing Specification (2),
Pending silicon characterization.
Values for device speed grade -7 and -8 will be available after characterization.
The maximum data rate that complies with duty cycle distortion of 45–55%.
The maximum data rate when taking duty cycle in absolute ps into consideration that may not comply with
45–55% duty cycle distortion. If the downstream receiver can handle duty cycle distortion beyond the 45–55%
range, you may use the higher data rate values from this column. You can calculate the duty cycle distortion as a
percentage using the absolute ps value. For example, for a data rate of 640 Mbps (UI = 1625 ps) and a t
ps, the duty cycle distortion is t
distortion of 42.3 - 57.7%.
Three-resistor LVDS is only supported at output pin of Column I/O (Bank 3, 4, 7 and 8).
(input clock frequency)
Table
Symbol
1–33:
DUTY
/(UI*2) *100% = 250 ps/(1625 *2) * 100% = 7.7%, which gives you a duty cycle
20–80%
80–20%
Modes
x10
x10
x8
x7
x4
x2
x1
x8
x7
x4
x2
x1
Min
10
10
10
10
10
10
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
-6 Speed Grade
(5)
Typ
(1)
(1)
Max
402.5
320
320
320
320
320
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(3)
Cyclone III Handbook
Max
402.5
320
320
320
320
320
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(4)
DUTY
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
MHz
MHz
MHz
MHz
MHz
MHz
Unit
ms
of 250
ps
ps
ps
ps
%
1–27