EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 110

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Clock Networks and PLLs in Cyclone III Devices
6–10
Cyclone III Device Handbook, Volume 1
From the clock sources listed above, only two clock input pins, two PLL
clock outputs, one DPCLK or CDPCLK pin, and one source from internal
logic can drive into any given clock control block, as shown in
Out of these five inputs to any clock control block, the two clock input
pins and two PLL outputs can be dynamically selected to feed a global
clock network. The clock control block supports static selection of the
signal from internal logic.
Figure 6–4
each side of the Cyclone III device periphery. The Cyclone III devices
support up to 20 of these clock control blocks and this allows for up to a
maximum of 20 global clocks in Cyclone III devices.
Figure 6–4. Clock Control Blocks on Each Side of the Cyclone III
Device
Note to
(1)
Global Clock Network Power Down
You can disable the Cyclone III global clock network (power down) by
both static and dynamic approaches. In the static approach, configuration
bits are set in the configuration file generated by the Quartus II software,
which automatically disables unused global clock networks. The
dynamic clock enable or disable feature allows internal logic to control
clock enable or disable of the global clock networks in the Cyclone III
device.
Clock Input Pins
Internal Logic
PLL Outputs
The left and right sides of the device have two
bottom of the device have four
Figure
CDPCLK
Note (1)
DPCLK
shows the simplified version of the five clock control blocks on
6–4:
2 or 4
4
5
2
5
Blocks on Each Side
Five Clock Control
of the Device
DPCLK
Control
Clock
Block
pins.
Altera Corporation- Preliminary
DPCLK
5
pins, and the top and
GCLK
Figure
March 2007
6–1.