EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 32

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Logic Elements and Logic Array Blocks in Cyclone III Devices
Figure 2–1. Cyclone III LE
2–2
Cyclone III Device Handbook, Volume 1
data 1
data 2
data 3
data 4
Register Feedback
LE Carry-In
Look-Up Table
(LUT)
LE Features
You can configure each LE's programmable register for D, T, JK, or SR
operation. Each register has data, clock, clock enable, and clear inputs.
Signals that use the global clock network, general-purpose I/O pins, or
any internal logic can drive the register’s clock and clear control signals.
Either general-purpose I/O pins or internal logic can drive the clock
enable. For combinational functions, the LUT output bypasses the
register and drives directly to the LE outputs.
Each LE has three outputs that drive the local, row, and column routing
resources. The LUT or register output can drive these three outputs
independently. Two LE outputs drive column or row and direct link
routing connections and one drives local interconnect resources. This
allows the LUT to drive one output while the register drives another
output. This feature, called register packing, improves device utilization
because the device can use the register and the LUT for unrelated
LE Carry-Out
Register Chain
Routing from
Chain
Carry
previous LE
(DEV_CLRn)
Chip-Wide
labclkena1
labclkena2
labclr1
labclr2
Reset
labclk2
labclk1
Synchronous
LAB-Wide
Load
Asynchronous
Synchronous
Clock Enable
Clear Logic
Clear Logic
Load and
Clock &
Select
Synchronous
LAB-Wide
Clear
Register Bypass
D
ENA
CLRN
Altera Corporation-Preliminary
Q
Register Chain
Output
Row, Column,
And Direct Link
Routing
Row, Column,
And Direct Link
Routing
Local
Routing
March 2007